Freescale Semiconductor Microcontrollers Clock Generation Module Option

HC08 Full Chip Simulation
Configuration Procedure
260 Microcontrollers Debugger Manual
Example
>ADCLR
Clear the input buffer for ADC simulation.
Clock Generation Module Option
In Full Chip Simulation Mode, this option lets you simulate all functionality of the Clock
Generation Module (CGM), including:
• Phase Locked Loop (PLL) generation
• Automatic lock detection
•Interrupt
• Acquisition
• Tracking
• Flag polling
Full Chip Simulation mode uses simulated External Oscillator Frequency change
command (XTAL) to allow the user to input the desired XTAL value. To check the
current value of the External Oscillator, Bus Frequency and CGMXCLK Frequency, open
the HCS08FCS menu, then select Clocks Module > Show MCU Clocks.
Figure 11.10 Show MCU Clocks Menu
Once you select the MCU Clocks Menu, the Cycles window containing all of the above-
mentioned Clock Frequencies appears.