HC08 Full Chip Simulation
Configuration Procedure
275
Microcontrollers Debugger Manual
The next two data bytes read are 22 and 23. If the microprocessor attempts to read
another byte, it gets an $FF value followed by a NACK signal (NACK because
nothing remains in the input buffer). The receiving device then generates a STOP
signal. A more exact input from a device designed to return two bytes is:
>IICDI ACK 22 ACK 23 NACK
MMIIC in master mode transmits to a slave. If the slave device acknowledges all
output bytes of the transmitting device, there is no need to specify an input packet.
If the master device is going to transmit an address and two bytes, the following
packet is equivalent to no packet:
>IICDI ACK ACK ACK
If, however, the slave receiver is designed to generate a NACK signal after the
second received data byte, the proper response packet is:
>IICDI ACK ACK NACK
The address result being the first ACK, the first data result being the second ACK,
and the second data byte being the NACK.
MMIIC in MASTER mode is not acknowledged by any Slave:
>IICDI NACK
If the NACK signal is entered before our master device transmits a START signal,
then the master device receives a NACK signal when it tries to read an
acknowledge after the address is output. The master device then generates a STOP
signal and releases the BUS.
MMIIC in SLAVE mode receives a Write from an external Master:
This example is for an external master which is writing to the microprocessor
configured to simulate the slave mode operation. The packet contains both START
and STOP signals which put the simulated device into the slave mode.
>IICDI START 55 AA 22 STOP
This input adds five values to the input queue, which is a packet from an external
master, including the following values:
• A start signal comes in.
• The address $55 comes in specifying a write (slave receive). The Address
Register of the current simulated device was previously set to $55.
• The data byte $AA comes in.
• The data byte $22 comes in.
•A STOP signal comes in.