Manuals / LSI / Computer Equipment / Computer Hardware

LSI 53C875A technical manual BAR0, BAR1

Models: 53C875A

1 328

Download 328 pages 47.1 Kb

Page 101

Registers: 0x10–0x13

Base Address Register Zero (I/O)

Read/Write

31																																		0
																	BAR0

0	0	0	0	0	0	0		0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0	1

							BAR0							Base Address Register Zero - I/O																		[31:0]

This base address register is used to map the operating register set into I/O space. The LSI53C875A requires 256 bytes of I/O space for this base address register. It has bit zero hardwired to one. Bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into I/O space. For detailed information on the operation of this register, refer to the PCI 2.2 specification.

Registers: 0x14–0x17

Base Address Register One (MEMORY)

Read/Write

31																																		0
																	BAR1

0	0	0	0	0	0	0		0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0	0

							BAR1							Base Address Register One																		[31:0]

This base address register maps SCSI operating registers into memory space. This device requires

1024 bytes of address space for this base register. This register has bits [9:0] hardwired to 0b0000000000. The default value of this register is 0x00000000. For detailed information on the operation of this register, refer to the PCI 2.2 specification.

PCI Configuration Registers

4-9

Image 101

LSI 53C875A technical manual BAR0, BAR1

Contents

C e m b e r 2 0 0 Technical ManualTrademark Acknowledgment Organization AudienceAnsi Conventions Used in This Manual PCI Special Interest GroupRevision Record Revision Date RemarksViPreface Contents Chapter Signal Descriptions Chapter Registers Figures Contents Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR XivContents Chapter General Description Typical LSI53C875A System Application Benefits of Ultra Scsi New Features in the LSI53C875ALSI53C875A Benefits Summary TolerANT TechnologyScsi Performance Ease of Use PCI PerformanceIntegration Scripts RAM FlexibilityTestability ReliabilityChapter Functional Description PCI Addressing PCI Functional DescriptionConfiguration Space PCI Bus Commands and Functions SupportedInterrupt Acknowledge Command PCI Bus Commands and Encoding Types for the LSI53C875ASpecial Cycle Command CBE30 Command Type Supported as Master Supported as Slave2.4 I/O Write Command 2.3 I/O Read CommandReserved Command Memory Read CommandMemory Read Line Command Memory Read Multiple CommandDual Address Cycle DAC Command PCI Functional Description Memory Write and Invalidate Command PCI Cache Mode Issuing Cache Commands Enabling Cache ModeMemory Write Caching Memory Read CachingHost Memory PCI Cache Mode AlignmentRead Example ExamplesWrite Example Write Example Memory-to-Memory Moves Scsi Functional DescriptionScripts Processor Phase Mismatch Handling in ScriptsInternal Scripts RAM Hardware Control of Scsi Activity LED 3 64-Bit Addressing in ScriptsDesigning an Ultra Scsi System Using the Scsi Clock QuadruplerPrefetching Scripts Instructions Load and Store Instructions Opcode Fetch Burst CapabilityScsi Loopback Mode Jtag Boundary Scan TestingParity Options Bit Name Location Description Bits Used for Parity Control and GenerationScsi Parity Control Scsi Parity Errors and InterruptsParity Checking/Generation DMA FifoData Paths DMA Fifo SectionsAsynchronous Scsi Send LSI53C875A Host Interface Scsi Data PathsSynchronous Scsi Send Synchronous Scsi Receive Asynchronous Scsi ReceiveScsi Termination Scsi Bus InterfaceRegulated Termination for Ultra Scsi Select/Reselect During Selection/ReselectionDetermining the Data Transfer Rate Synchronous OperationDetermining the Synchronous Transfer Rate Scsi Control Three SCNTL3 Register, Bits 20 CCF20 Scsi Control Three SCNTL3 Register, Bits 64 SCF20Scsi Transfer Sxfer Register, Bits 75 TP20 Ultra Scsi Synchronous Data TransfersRegisters Interrupt HandlingPolling and Hardware Interrupts Functional Description Fatal vs. Nonfatal Interrupts Masking Stacked Interrupts Halting in an Orderly Fashion Read Interrupt Status Zero ISTAT0 Sample Interrupt Service RoutineChained Block Moves Wide Scsi Send Bit Block Move and Chained Block Move InstructionsSodl Register Wide Scsi Receive BitSwide Register Chained Block Move Scripts Instruction Parallel ROM Interface MAD31 Available Memory Space Parallel ROM SupportSerial Eeprom Interface Default Download ModeNo Download Mode Power ManagementMode a Serial Eeprom Data Format Byte Name DescriptionPower State D1 Power State D0Power States Configuration Register BitsPower State D3 Power State D2Functional Description Chapter Signal Descriptions LSI53C875A Functional Signal Grouping LSI53C875A Functional Signal GroupingInternal Pull-ups on LSI53C875A Signals Signal DescriptionsSignal Name Pull-up Current Conditions for Pull-up LSI53C875A Internal Pull-upsSystem Signals PCI Bus Interface SignalsSystem Signals Type Strength DescriptionBus Command and Byte Enables are Address and Data SignalsAddress and Data Signals Initialization Device Select is used as a chip select Interface Control SignalsInterface Control Signals Error Reporting Signals Arbitration SignalsArbitration Signals Error Reporting SignalsInterrupt Signal Scsi Bus Interface SignalsScsi Bus Interface Signal Interrupt SignalScsi Control Signals Scsi SignalsScsi Signals 10 Scsi Control Signals11 Gpio Signals Gpio SignalsScsi General Purpose I/O pin. Optionally Scsi General Purpose I/O pin. This pin12 ROM Flash and Memory Interface Signals ROM Flash and Memory Interface SignalsMemory Address/Data Bus. This bus is used Test Interface Signals13 Test Interface Signals 14 Power and Ground Signals Power and Ground SignalsMAD Bus Programming 15 Decode of MAD PinsMAD Bus Programming Signal Descriptions Chapter Registers PCI Configuration RegistersVIDVendor ID150 RegistersVendor ID Read Only Enable Parity Error Response Command Read/WriteDevice ID Read Only DIDDevice ID150EBM WIEEMS EISSSE DPERMA RTADPR RegisterRevision ID Rev ID Read Only RIDRevision ID70Register 0x0C Registers 0x09-0x0BRegister 0x0F Register 0x0DRegister 0x0E BAR1 BAR0Registers 0x1C-0x27 Registers 0x18-0x1BRegisters 0x28-0x2B Registers 0x2C-0x2DSubsystem ID Read Only Registers 0x2E-0x2FSID Subsystem ID 150Expansion ROM Base Address 310 Expansion ROM Base Address Read/WriteErba Register 0x3C Registers 0x35-0x3BCapabilities Pointer Read Only CPCapabilities Pointer70 Interrupt Line Read/Write ILInterrupt Line70Register 0x3E Register 0x3DRegister 0x3F MGMINGNT70Pmes D1S D2SDSI APSDslt DsclPEN Bridge Support Extensions Pmcsrbse Read OnlyDATAData70 Scsi RegistersData Read Only Scsi Register Address Map Arbitration Mode ARB10 Arbitration Mode Bits 1Scsi Control Zero SCNTL0 Read/Write Simple ArbitrationStart Start Sequence5 Full Arbitration, Selection/ReselectionAAP WatnEPC DHP EXCADB RST CONAesp IarbSSTStart Scsi Transfer0 Scsi Control Two SCNTL2 Read/Write Chained ModeSDU Scsi Disconnect UnexpectedSlphben SlpmdWSS VUE0WSRWide Scsi Receive0 Ultra Scsi EnableScsi Control Three SCNTL3 Read/Write USESCF20 Synchronous Clock Conversion Factor Enable Wide ScsiEWS CCF20 Clock Conversion FactorENC RRESRE TP20 Scsi Synchronous Transfer Period Scsi Transfer Sxfer Read/WriteBits Period ns Mbytes/s Synch CLK MHzTransfer Rate MO40 Max Scsi Synchronous Offset Synchronous Offset Maximum Synchronous OffsetEncoded Destination Scsi ID Scsi Destination ID Sdid Read/WriteGeneral Purpose GPREG0 Read/Write GpioSfbr Scsi First Byte Received70 Scsi First Byte Received Sfbr Read/WriteACK REQBSY SELRegister 0x0B Register 0x0AVAL EnidSACK/ Status SREQ/ StatusSBSY/ Status SSEL/ StatusAbrt MdpeSSI SIRScsi Registers OLF ILFORF WOA AIPLOA SSTAT2 bit Scsi Synchronous Data Fifo Word CountBytes or Words SDP0L OLF1 ILF1ORF1 Ldsc SPL1SDP1 DSAAbort Operation Srst Software Reset6Interrupt Status Zero ISTAT0 Read/Write Sigp Signal ProcessSEM SemaphoreDipdma Interrupt Pending0 Sipscsi Interrupt Pending1Syncirqd FlshSrun MBOX0 Mailbox Zero70 Mailbox Zero MBOX0 Read/WriteMailbox One MBOX1 Read/Write MBOX1 Mailbox One70FMTByte Empty in DMA FIFO70 Chip Test Zero CTEST0 Read/WriteChip Test One CTEST1 Read Only FFLByte Full in DMA FIFO70CIO Register 0x1ADdir Dack TeopDreq CLF Register 0x1BFLF DMA Fifo Dfifo Registers 0x1C-0x1FTemp 58Registers FBL3 BdisZSD SrtmChip Test Five CTEST5 Read/Write FBL20 Fifo Byte ControlAdck Clock Address IncrementorDFS BbckMasr BL2DBC Dfdma FIFO70Dcmd DMA Command70 DMA Command Dcmd Read/WriteDSP Registers 0x2C-0x2FDnad Dsps DMA Scripts Pointer Save310 DMA Scripts Pointer Save Dsps Read/WriteScratch Register a Scratcha Read/Write Scratcha Scratch Register a 310BL10 Burst Length DMA Mode Dmode Read/WriteDestination I/O Memory Enable Source I/O Memory EnableERLEnable Read Line3 SiomBurst Opcode Fetch Enable Enable Read MultipleErmp BOFMaster Data Parity Error Bus Fault DMA Interrupt Enable Dien Read/WriteScripts Interrupt Instruction Received Reserved Illegal Instruction DetectedRegister 0x3B Register 0x3AClse PFFIrqmirq Mode3 Single Step ModeSSM STDStart DMA Operation2 IRQ DisableIrqd COMLSI53C700 Compatibility0Adder Registers 0x3C-0x3F0x40 RSL CMPSGE UDCGEN STOScsi Interrupt Status Zero SIST0 Read Only HTHHandshake-to-Handshake Timer Expired0Initiator Mode Phase Mismatch Target Mode SATN/ Active This bit is set when an arbitration only or full arbitration Scsi RST/ Received Parity ErrorPAR Scsi Interrupt Status One SIST1 Read OnlyHTH Handshake-to-Handshake Timer ExpiredScsi Longitudinal Parity Slpar Read/Write Slpar Scsi Longitudinal Parity70Data Bytes Running Slpar Scsi Wide Residue Swide Read/Write Memory Access Control Macntl Read/WriteSwide Scsi Wide Residue70 TYPDRD DWRPscpt Scpts ScriptsGpiogpio Enable10 Gpio EnableScsi Timer Zero STIME0 Read/Write HTH30 Handshake-to-HandshakeTimer PeriodSEL30 Selection Time-Out30 Hthsf HthbaGensf Register 0x4B Register 0x4ASsaid Register 0x4CSLT ARTSclk Register 0x4DISO QENQsel Register 0x4ESCE ROFAWS SZMEXT LOWSTR Register 0x4FTimer Test Mode Disable Single Initiator ResponseS16 Bit System TTMSidlscsi Input Data Latch150 STWScsi Input Data Latch Sidl Read Only Lock Register 0x53Chip Control 0 CCNTL0 Read/Write Enable Phase Mismatch JumpEnpmj Pmjctl Jump Control6Dils EnndjDisfc 64TIMOD ZmodeDdac EN64TIBMV Enable 64-Bit Direct BmovEN64DBMV Scsi Bus Data Lines Sbdl Read OnlyRegister 0x5A-0x5B 64-Bit Scripts SelectorsRegisters 0x5C-0x5F Registers 0x60-0x9FMemory Move Read Selector Mmrs Read/Write Registers 0xA0-0xA3Mmrs Memory Move Read Selector MmrsRegisters 0xA8-0xAB Registers 0xA4-0xA7Mmws SFSRegisters 0xB0-0xB3 Registers 0xAC-0xAFDRS SbmsRegisters 0xB4-0xB7 Phase Mismatch Jump RegistersRegisters 0xB8-0xBB Registers 0xBC-0xBFRegisters 0xC4-0xC7 Registers 0xC0-0xC3PMJAD1 PMJAD2RBC Registers 0xC8-0xCBRegisters 0xCC-0xCF Entry Storage Address ESA Read/Write Registers 0xD0-0xD3ESA Entry Storage Address 310SBC Registers 0xD4-0xD7Registers 0xD8-0xDA Registers 0xDC-0xDF Register 0xDBRegisters 0xE0-0xFF CsbcScsi Scripts Low Level Register Interface ModeHigh Level Scsi Scripts Mode Instruction Description Sample OperationScripts Instructions Scsi Scripts Instruction Set Scripts Overview First Dword Block Move InstructionTable Indirect Bit Addressing Direct AddressingTIA Command Not Used Don’t Care OPC Instruction Defined Target ModeOPCOpCode27 Initiator Mode SCSIP20 Scsi Phase2624 TC230 Transfer Counter230 Scsi Information Transfer PhaseScsi Phase I/O Instruction Target Mode Initiator ModeSecond Dword Start Address 310OPC20 OpCode 2927 IT10 Instruction Type I/O Instruction 3130Reselect Instruction Instruction DefinedWait Select Instruction Disconnect InstructionSet Instruction Clear InstructionSelect Instruction Wait Reselect Instruction Wait Disconnect InstructionTITable Indirect Mode25 Relative Addressing ModeTable Indirect DirectRelative BitTable Relative Command Table Offset Absolute Jump OffsetSet/Clear Satn Set/Clear Sack ReservedIT10 Instruction Type Read/Write Instruction 3130 Read/Write InstructionsO20 Operator 2624 Use data8/SFBRA60 Register Address A60 2216 Read-Modify-Write CyclesRead/Write Instructions Move To/From Sfbr CyclesTransfer Control Instructions Jump Instruction IT10 Instruction Type Transfer Control 3130Transfer Control Instructions Return Instruction Call InstructionInterrupt-on-the-Fly Instruction Interrupt InstructionRARelative Addressing Mode23 Scsi Phase ComparisonsJump/Call an Absolute Address Jump/Call a Relative AddressJump If True/False Bit 2 is assertedJMP Wait for Valid Phase Compare PhaseCompare Data WVPDCV Memory Move InstructionsData Compare Value Jump Address 310No Flush IT20 Instruction Type Memory Move 3129Reserved 2825 Dsps Register 310 Read/Write System Memory from ScriptsThird Dword Load and Store InstructionsTemp Register 310 Bit A1 Bit A0 Number of Bytes Allowed to Load and StoreDSA Relative IT20 Instruction Type 3129Reserved 2726 No Flush Store instruction only Bit Source DestinationDMA Control Dcntl register is set This bit has no effect unless the Prefetch Enable bitScsi Scripts Instruction Set DC Characteristics Chapter Electrical SpecificationsAbsolute Maximum Stress Ratings1 Symbol Parameter Min Max Unit Test ConditionsOperating Conditions1 Input CapacitanceBidirectional Signals-GPIO0FETCH/, GPIO1MASTER/, GPIO24 Bidirectional Signals-MAD70, MAS/10, MCE/, MOE/, MWEOutput Signal-TDO Output Signal-SERR TolerANT Technology Electrical CharacteristicsOutput Signals-IRQ/, MAC/TESTOUT, REQ Pqfp Symbol Parameter Min1 Max Unit Test ConditionsRise and Fall Time Test Condition Input Current as a Function of Input Voltage 12 External Clock1 AC CharacteristicsSymbol Parameter Min Max Unit Interrupt Output Reset InputPCI and External Memory Interface Timing Diagrams Electrical Specifications Target Timing 15 PCI Configuration Register ReadPCI Configuration Register Read 10 PCI Configuration Register Write 16 PCI Configuration Register Write11 32-Bit Operating Register/SCRIPTS RAM Read 17 32-Bit Operating Register/SCRIPTS RAM Read12 64-Bit Address Operating Register/SCRIPTS RAM Read 18 64-Bit Address Operating Register/SCRIPTS RAM Read13 32-Bit Operating Register/SCRIPTS RAM Write 19 32-Bit Operating Register/SCRIPTS RAM Write14 64-Bit Address Operating Register/SCRIPTS RAM Write 20 64-Bit Address Operating Register/SCRIPTS RAM Write21 Nonburst Opcode Fetch, 32-Bit Address and Data Initiator Timing15 Nonburst Opcode Fetch, 32-Bit Address and Data 22 Burst Opcode Fetch, 32-Bit Address and Data 16 Burst Opcode Fetch, 32-Bit Address and Data 23 Back-to-Back Read, 32-Bit Address and Data 17 Back-to-Back Read, 32-Bit Address and Data 24 Back-to-Back Write, 32-Bit Address and Data 18 Back-to-Back Write, 32-Bit Address and Data 25 Burst Read, 32-Bit Address and Data 19 Burst Read, 32-Bit Address and Data 26 Burst Read, 64-Bit Address and Data 20 Burst Read, 64-Bit Address and Data 27 Burst Write, 32-Bit Address and Data 21 Burst Write, 32-Bit Address and Data 28 Burst Write, 64-Bit Address and 32-Bit Data 22 Burst Write, 64-Bit Address and 32-Bit Data 29 External Memory Read External Memory Timing23 External Memory Read STOP/ Driven by LSI53C875A 30 External Memory Write External Memory Write timings start on 24 External Memory Write Data Byte Enable Address out from MOE/, MCE/ High Driven by LSI53C875A Higher Valid Write Data CBE30 Byte Enable Data Byte Enable Out Lower Address Data LSI53C875A-Data Data Byte Enable Data Out Slow Memory ≤ 128 Kbytes Read Cycle Symbol Parameter Min30 Slow Memory ≤ 128 Kbytes Write Cycle Slow Memory ≤ 128 Kbytes Write Cycle≤ 64 Kbytes ROM Read Cycle 32 ≤ 64 Kbyte ROM Write Cycle ≤ 64 Kbyte ROM Write Cycle37 Initiator Asynchronous Send Scsi Timing Diagrams34 Initiator Asynchronous Receive 38 Initiator Asynchronous Receive35 Target Asynchronous Send 39 Target Asynchronous Send41 SCSI-1 Transfers 5.0 Mbytes 40 Target Asynchronous ReceiveSymbol Parameter Min Max Unit 37 Initiator and Target Synchronous Transfer 38 LSI53C875A 160-Pin Pqfp Mechanical Drawing Package DiagramsPin Pqfp P3 Mechanical Drawing Sheet 2 44 160 Pqfp Pin List by Location Signal PinPin BGA Mechanical Drawing NC1 45 169 BGA Pin List by LocationAppendix a Register Summary Table A.2 LSI53C875A Scsi Register Map Register Summary Scratch Registers C-RSCRATCHC-SCRATCHR Table A.2 LSI53C875A Scsi Register Map Register Summary Appendix B External Memory Interface Diagram Examples Figure B.2 64 Kbyte Interface with 150 ns Memory External Memory Interface Diagram Examples Figure B.4 512 Kbyte Interface with 150 ns Memory Index SymbolsIX-2Index SGE 4-74,4-77 SI NumericsIX-4Index IX-5 IX-6Index IX-7 IX-8Index IX-9 IX-10Index Customer Feedback Excellent Good Average Fair Poor Reader’s CommentsCalifornia Distributors by StateNew York Direct Sales Representatives by State Component and HAB North America Sales Offices and Design Resource CentersKorea Australia Hong Kong International Distributors