5.4.1 First Dword

31 30 29

27

26

25

24

23

20 19

16 15

 

11 10

 

9

8

7

6

5

4

3

2

0

DMA Command (DCMD)

 

 

 

 

DMA Byte Counter (DBC) Register

 

 

 

 

 

 

 

 

Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IT[1:0]

OPC[2:0]

RA

TI

Sel

R

 

ENDID[3:0]

 

R

 

CC

TM

R

 

ACK

R

 

ATN

R

 

0 1

x x x

x

x

x

0 0 0 0

x x x x

0 0 0 0 0

x

x

0 0

x

0 0

 

x

0 0 0

 

 

 

 

 

IT[1:0]

 

Instruction Type - I/O Instruction

 

 

 

 

 

[31:30]

 

 

 

 

 

 

 

 

 

The IT bit configuration (01) defines an I/O Instruction

 

 

 

 

 

 

 

 

 

 

Type.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPC[2:0]

 

 

OpCode

 

 

 

 

 

 

 

 

 

 

 

 

[29:27]

 

 

 

 

 

 

 

 

 

The OpCode bit configurations define the I/O operation

 

 

 

 

 

 

 

 

 

performed but the OpCode bit meanings change in Target

 

 

 

 

 

 

 

 

 

mode compared to Initiator mode. OpCode bit

 

 

 

 

 

 

 

 

 

 

 

configurations (101, 110, and 111) are considered

 

 

 

 

 

 

 

 

 

 

Read/Write instructions, and are described in Section

 

 

 

 

 

 

 

 

 

 

5.5, “Read/Write Instructions.”This section describes

 

 

 

 

 

 

 

 

 

 

Target mode operations.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Target Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPC2

OPC1

OPC0

 

Instruction Defined

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

 

Reselect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

 

Disconnect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

0

 

Wait Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

 

Set

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

 

Clear

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reselect Instruction

The LSI53C875A arbitrates for the SCSI bus by asserting the SCSI ID stored in the SCSI Chip ID (SCID) register. If it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status.

If the LSI53C875A wins arbitration, it attempts to reselect the SCSI device whose ID is defined in the destination ID field of the instruction. Once the LSI53C875A wins arbitration, it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register.

5-14

SCSI SCRIPTS Instruction Set

Page 214
Image 214
LSI 53C875A IT10 Instruction Type I/O Instruction 3130, OPC20 OpCode 2927, Reselect Instruction, Instruction Defined