LSI 53C875A technical manual Initiator Timing, Nonburst Opcode Fetch, 32-Bit Address and Data

6.4.2 Initiator Timing

The tables and figures in this section describe LSI53C875A initiator timings.

Table 6.21 Nonburst Opcode Fetch, 32-Bit Address and Data

Symbol	Parameter	Min	Max	Unit
t1	Shared signal input setup time	7	–	ns
t2	Shared signal input hold time	0	–	ns
t3	CLK to shared signal output valid	2	11	ns
t4	Side signal input setup time	10	–	ns
t5	Side signal input hold time	0	–	ns
t6	CLK to side signal output valid	2	12	ns
t7	CLK HIGH to GPIO0_FETCH/ LOW	–	20	ns
t8	CLK HIGH to GPIO0_FETCH/ HIGH	–	20	ns
t9	CLK HIGh to GPIO1_MASTER/ LOW	–	20	ns
t10	CLK HIGH to GPIO1_MASTER/ HIGH	–	20	ns

PCI and External Memory Interface Timing Diagrams 6-19