LSI 53C875A 6.4.2 Initiator Timing

PCI and External Memory InterfaceTiming Diagrams 6-19
6.4.2 Initiator Timing
The tables and figures in this section describe LSI53C875A initiator
timings.
Table 6.21 Nonburst Opcode Fetch, 32-Bit Address and Data
Symbol Parameter Min Max Unit
t1Shared signal input setuptime 7 – ns
t2Shared signal input hold time 0 – ns
t3CLK to shared signal output valid 2 11 ns
t4Side signal input setup time 10 – ns
t5Side signal input hold time 0 – ns
t6CLK to side signal output valid 2 12 ns
t7CLK HIGH to GPIO0_FETCH/ LOW – 20 ns
t8CLK HIGH to GPIO0_FETCH/ HIGH – 20 ns
t9CLK HIGh to GPIO1_MASTER/ LOW – 20 ns
t10 CLK HIGH to GPIO1_MASTER/ HIGH – 20 ns