Register: 0x34

Capabilities Pointer

Read Only

7

0

CP

0

1

0

0

0

0

0

0

CPCapabilities Pointer[7:0]

This register indicates that the first extended capability register is located at offset 0x40 in the PCI Configuration.

Registers: 0x35–0x3B

Reserved

Register: 0x3C

Interrupt Line

Read/Write

7

0

IL

0

0

0

0

0

0

0

0

ILInterrupt Line[7:0]

This register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it configures the system. The value in this register tells which input of the system interrupt controller(s) the device’s interrupt pin is connected to. Values in this register are specified by system architecture.

PCI Configuration Registers

4-13

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LSI 53C875A technical manual Registers 0x35-0x3B, Register 0x3C, Capabilities Pointer Read Only CPCapabilities Pointer70