Table 6.33

Slow Memory (128 Kbytes) Read Cycle

 

 

 

 

 

 

 

 

Symbol

Parameter

Min

Max

Unit

 

 

 

 

 

t11

Address setup to MAS/ HIGH

25

ns

t12

Address hold from MAS/ HIGH

15

ns

t13

MAS/ pulse width

25

ns

t14

MCE/ LOW to data clocked in

150

ns

t15

Address valid to data clocked in

205

ns

t16

MOE/ LOW to data clocked in

100

ns

t17

Data hold from address, MOE/, MCE/ change

0

ns

t18

Address out from MOE/, MCE/ HIGH

50

ns

t19

Data setup to CLK HIGH

5

ns

Figure 6.29 Slow Memory (128 Kbytes) Read Cycle

CLK

MAD

(Address driven by LSI53C875A;

Data driven by Memory)

MAS1/ (Driven by LSI53C875A)

MAS0/ (Driven by LSI53C875A)

MCE/ (Driven by LSI53C875A)

MOE/ (Driven by LSI53C875A)

MWE/ (Driven by LSI53C875A)

Valid Read Data

 

 

 

t17

Higher

Middle

Lower

 

Address

Address

Address

 

 

t12

 

t

t11

 

 

19

 

 

 

 

t13

t15

 

 

 

 

 

 

t14

 

 

 

t16

t18

6-48

Electrical Specifications

Page 286
Image 286
LSI 53C875A technical manual Slow Memory ≤ 128 Kbytes Read Cycle, Symbol Parameter Min