LSI 53C875A technical manual IX-8Index

reset 3-4input 6-10

SCSI offset (ROF) 4-89response ID one (RESPID1) 4-86response ID zero (RESPID0) 4-86return instruction 5-27

revision ID (RID) 4-6

ROM

flash and memory interface signals 3-11pin 2-49

RST/ 3-4

S

SACK 2-42

SACK/ status (ACK) 4-39SACs 2-19

SATN/ status (ATN) 4-39SBSY/ status (BSY) 4-39SC_D/ status (C_D) 4-39SCLK 3-8

(SCLK) 4-88

quadrupler enable (QEN) 4-88quadrupler select (QSEL) 4-89

SCNTL0 2-25SCNTL1 2-24, 2-25SCNTL3 2-36scratch

byte register (SBR) 4-70register A (SCRATCHA) 4-65register B (SCRATCHB) 4-99

registers C–R (SCRATCHC–SCRATCHR) 4-99script fetch selector (SFS) 4-101

SCRIPTS (SCPTS) 4-82instruction 2-46

interrupt instruction received (SIR) 4-40, 4-69processor 2-17

internal RAM for instruction storage 2-18performance 2-17

RAM 2-3,2-18 running (SRUN) 4-51

SCSI

ATN condition - target mode (M/A) 4-73bus control lines (SBCL) 4-38

bus data lines (SBDL) 4-98bus interface 2-32

byte count (SBC) 4-107C_D/ signal (C_D) 4-45chip ID (SCID) 4-30clock 3-8

control enable (SCE) 4-89control one (SCNTL1) 4-23control three (SCNTL3) 4-28control two (SCNTL2) 4-26control zero (SCNTL0) 4-20data high impedance (ZSD) 4-59destination ID (SDID) 4-35disconnect unexpected (SDU) 4-26encoded destination ID 5-20FIFO test read (STR) 4-91

FIFO test write (STW) 4-93first byte received (SFBR) 4-36functional description 2-16GPIO signals 3-10

gross error (SGE) 4-74, 4-77

I_O/ signal (I/O) 4-45

input data latch (SIDL) 4-93instructions

block move 5-6I/O 5-13read/write 5-22

interface signals 3-8

interrupt enable one (SIEN1) 4-75interrupt enable zero (SIEN0) 4-73interrupt pending (SIP) 4-50interrupt status one (SIST1) 4-78interrupt status zero (SIST0) 4-76interrupts 2-42

isolation mode (ISO) 4-88longitudinal parity (SLPAR) 4-79loopback mode 2-23loopback mode (SLB) 4-89low level mode (LOW) 4-90MSG/ signal (MSG) 4-45output control latch (SOCL) 4-37output data latch (SODL) 4-94parity control 2-26

parity error (PAR) 4-75performance 1-5phase 5-11, 5-28

phase mismatch - initiator mode 4-73reset condition (RST) 4-75

RST/ received (RST) 4-78RST/ signal (RST) 4-43SCRIPTS operation 5-2

sample instruction 5-3SDP0/ parity signal (SDP0) 4-43SDP1 signal (SDP1) 4-47selected as ID (SSAID) 4-87selector ID (SSID) 4-38

serial EEPROM access 2-50signals 3-9

status one (SSTAT1) 4-43status two (SSTAT2) 4-46status zero (SSTAT0) 4-42synchronous offset maximum (SOM) 4-88synchronous offset zero (SOZ) 4-87synchronous transfer period (TP[2:0]) 4-31termination 2-32

test four (STEST4) 4-94test one (STEST1) 4-88test three (STEST3) 4-91test two (STEST2) 4-89test zero (STEST0) 4-87timer one (STIME1) 4-85timer zero (STIME0) 4-83TolerANT technology 1-4transfer (SXFER) 4-31

true end of process (TEOP) 4-55Ultra SCSI 2-20

valid (VAL) 4-38

wide residue (SWIDE) 4-81SCSI-2

fast transfers

10.0Mbytes (8-bit transfers) 40 MHz clock 6-56

20.0Mbytes (16-bit transfers) 40 MHz clock 6-56

SCTRL signals 3-9SD[15:0] 3-9

second dword 5-13,5-21,5-23,5-32,5-34,5-37

IX-8Index