LSI 53C875A - page 32

2-10 Functional Description

software enabled or disabled to allow the user full flexibility in using these

commands.

2.1.3.1 Enabling Cache Mode

In order to enable the cache logic to issue PCI cache commands

(Memory Read Line, Memory Read Multiple, and Memory Wr ite and

Invalidate) on any given PCI master operation the following conditions

must be met:

•The Cache Line Size Enable bit in the DMA Control (DCNTL) register

must be set.

•The PCI CacheLineSizeregister must contain a valid binary cache

size, i.e. 2, 4, 8, 16, 32, 64, or 128 Dwords. Only these values are

considered valid cache sizes.

•The programmed burst size (in Dwords) must be equal to or greater

than the CacheLineSizeregister. The DMA Mode (DMODE) register

bits [7:6] and Chip TestFive (CTEST5) bit 2 are the burst length bits.

•The part must be doing a PCI Master transfer. The following PCI

Master transactions do not utilize the PCI cache logic and thus no

PCI cache command is issued during these types of cycles: a

nonprefetch SCRIPTS fetch, a Load/Store data transfer, or a data

flush operation. All other types of PCI Master transactions will utilize

the PCI cache logic.

The above conditions must be met for the cache logic to control the type

of PCI cache command that is issued, along with any alignment that may

be necessary during write operations. If these conditions are not metfor

any given PCI Master transaction, a Memory Read or Memory Write is

issued and no cache write alignment is done.

2.1.3.2 Issuing Cache Commands

In order to issue each type of PCI cache command, the corresponding

enable bit must be set (2 bits in the case of Memory Write and

Invalidate). These bits are detailed below:

•Toissue Memor y Read Line commands, the Read Line enable bit in

the DMA Mode (DMODE) register must be set.

Contents

Main Page Preface Page Page Contents Page Page Page Page Page Page Page Chapter 1 General Description 1-2 General Description Figure 1.1 Typical LSI53C875A System Application Figure 1.2 Typical LSI53C875A Board Application 1.1 New Features in the LSI53C875A 1.2 Benefits of Ultra SCSI 1.3 TolerANTTechnology 1.4 LSI53C875A Benefits Summary 1.4.1 SCSI Performance 1.4.2 PCI Performance 1.4.3 Integration 1.4.4 Ease of Use 1.4.5 Flexibility 1.4.6 Reliability 1.4.7 Testability Chapter 2 Functional Description 2-2 Functional Description Figure 2.1 LSI53C875A Block Diagram 2.1 PCI Functional Description The LSI53C875A implementsa PCI-to-Wide Ultra SCSI controller. 2.1.1 PCI Addressing There are three physical PCI-defined address spaces: 2.1.2 PCI Bus Commands and Functions Supported Page Page Page Page Page 2.1.3 PCI Cache Mode Page Page Tabl e 2.2 describes PCI cache mode alignment. Table 2.2 PCI Cache Mode Alignment Page Read Example 3 Burst = 16 Dwords, Cache Line Size = 8 Dwords: Write Example 1 Burst=4Dwords,CacheLineSize= 4Dwords: Write Example 2 Burst=8Dwords,CacheLineSize= 4Dwords: 2.2 SCSI Functional Description 2.2.1 SCRIPTS Processor 2.2.2 Internal SCRIPTS RAM 2.2.3 64-Bit Addressing in SCRIPTS 2.2.4 Hardware Control of SCSI Activity LED 2.2.5 Designing an Ultra SCSI System 2.2.6 Prefetching SCRIPTS Instructions 2.2.7 Opcode Fetch Burst Capability 2.2.8 Load and Store Instructions 2.2.9 JTAG Boundary Scan Testing 2.2.10 SCSI Loopback Mode 2.2.11 Parity Options Table 2.3 Bits Used for Parity Control and Generation Table 2.4 SCSI Parity Control Table2.5 SCSI Parity Errorsand Interrupts SCSI Functional Description 2-27 Figure 2.2 Parity Checking/Generation 2.2.12 DMA FIFO Page Page Page Page 2.2.13 SCSI Bus Interface SCSI Functional Description 2-33 Figure 2.5 Regulated Termination for Ultra SCSI 2.2.14 Select/Reselect During Selection/Reselection TERML1 TERML2 TERML3 TERML4 TERML5 TERML6 TERML7 TERML8 TERML9 2.2.15 Synchronous Operation SCSI Functional Description 2-35 Figure 2.6 Determining the Synchronous TransferRate Page 2.2.16 Interrupt Handling Page Page Page Page Page Page Page Page Page Page 2.3 Parallel ROM Interface Page 2.4 Serial EEPROM Interface 2.4.1 Default DownloadMode 2.4.2 No Download Mode 2.5 Power Management 2.5.1 Power State D0 2.5.2 Power State D1 2.5.3 Power State D2 2.5.4 Power State D3 Page Chapter 3 Signal Descriptions 3-2 Signal Descriptions 3.1 LSI53C875A Functional Signal Grouping PCIBus Interface 3.2 Signal Descriptions 3.2.1 Internal Pull-ups on LSI53C875A Signals 3.3 PCI Bus Interface Signals 3.3.1 SystemSignals 3.3.2 Address and Data Signals Tabl e 3.3 describes Address and Data signals. Table 3.3 Address and Data Signals 3.3.3 Interface Control Signals Tabl e 3.4 describes the Interface Control signals. Table 3.4 Interface Control Signals 3.3.4 Arbitration Signals Tabl e 3.5 describes Arbitration signals. Tabl e 3.6 describes the Error Reporting signals. 3.3.5 Error Reporting Signals Table 3.5 Arbitration Signals 3.4 SCSI Bus Interface Signals 3.4.1 SCSI Bus Interface Signal 3.4.2 SCSI Signals Tabl e 3.9 describes the SCSI signals. Tabl e 3.10 describes the SCSIControl signals. 3.4.3 SCSI Control Signals Table3.9 SCSI Signals 3.5 GPIO Signals Tabl e 3.11 describes the SCSI GPIO signals. Table 3.11 GPIO Signals 3.6 ROM Flash and Memory Interface Signals 3.7 Test Interface Signals Tabl e 3.13 describes Test Interface signals. Table 3.12 ROM Flash and Memory Interface Signals (Cont.) Table 3.13 Test Interface Signals 3.8 Power and Ground Signals Tabl e 3.14 describes the Power and Ground sig nals. Table 3.14 Power and Ground Signals 3.9 MAD Bus Programming Page Page Chapter 4 Registers 4.1 PCI Configuration Registers Registers:0x000x01 Registers:0x020x03 Registers:0x040x05 Page Registers:0x060x07 Register: 0x08 Registers:0x090x0B Register: 0x0C Register: 0x0D Register: 0x0E Register: 0x0F Registers:0x100x13 Registers:0x140x17 Registers:0x180x1B Registers:0x1C0x27 Registers:0x280x2B Registers:0x2C0x2D Registers:0x2E0x2F Registers:0x300x33 Register: 0x34 Registers:0x350x3B Register: 0x3C Register: 0x3D Register: 0x3E Register: 0x3F Register: 0x40 Register: 0x41 Registers:0x420x43 Registers:0x440x45 Register: 0x46 Register: 0x47 4.2 SCSI Registers SCSI Registers 4-19 Table 4.2 SCSI Register Address Map Register: 0x00 Page Page Register: 0x01 Page Page Register: 0x02 Page Register: 0x03 Page Register: 0x04 Register: 0x05 Page Page Table 4.5 Maximum Synchronous Offset Register: 0x06 Register: 0x07 Register: 0x08 Register: 0x09 Register: 0x0A Register: 0x0B Register: 0x0C Page Page Register: 0x0D Register: 0x0E Page Page Register: 0x0F Registers:0x100x13 Register: 0x14 Page Page Register: 0x15 Register: 0x16 Register: 0x17 Register: 0x18 Register: 0x19 Register: 0x1A Page Register: 0x1B Registers:0x1C0x1F Register: 0x20 Page Register: 0x21 Register: 0x22 Page Register: 0x23 Registers:0x240x26 Register: 0x27 Registers:0x280x2B Registers:0x2C0x2F Registers:0x300x33 Registers:0x340x37 Register: 0x38 Page Page Register: 0x39 Register: 0x3A Register: 0x3B Page Page Registers:0x3C0x3F Register: 0x40 Page Register: 0x41 Register: 0x42 Page Register: 0x43 Register: 0x44 Page Register: 0x45 Register: 0x46 Register: 0x47 Register: 0x48 Page Register: 0x49 Register: 0x4A Register: 0x4B Register: 0x4C Register: 0x4D Register: 0x4E Page Register: 0x4F Page Registers:0x500x51 Register: 0x52 Register: 0x53 Registers:0x540x55 Register: 0x56 Page Register: 0x57 Registers:0x580x59 Register: 0x5A0x5B Registers:0x5C0x5F Registers:0x600x9F 4.3 64-Bit SCRIPTS Selectors Registers:0xA00xA3 Registers:0xA40xA7 Registers:0xA80xAB Registers:0xAC0xAF Registers:0xB00xB3 Registers:0xB40xB7 Registers:0xB80xBB Registers:0xBC0xBF 4.4 Phase Mismatch Jump Registers Registers:0xC00xC3 Registers:0xC40xC7 Registers:0xC80xCB Registers:0xCC0xCF Registers:0xD00xD3 Registers:0xD40xD7 Registers:0xD80xDA Register: 0xDB Registers:0xDC0xDF Registers:0xE00xFF Chapter 5 SCSI SCRIPTS Instruction Set 5.1 Low Level Register Interface Mode 5.2 High Level SCSI SCRIPTS Mode 5.2.1 Sample Operation Page High Level SCSI SCRIPTS Mode 5-5 Figure 5.1 SCRIPTS Overview I P 5.3 Block Move Instruction 5.3.1 First Dword Page Page Page Page Page Page 5.3.2 Second Dword 5.4 I/O Instruction 5.4.1 First Dword Page Page Page Page Page Page 5.4.2 Second Dword 5.5 Read/Write Instructions 5.5.1 First Dword 5.5.2 Second Dword 5.5.3 Read-Modify-Write Cycles 5.5.4 Move To/From SFBR Cycles any chip register. or SHIFT RIGHT operators. similar instructions are used to check the value. 5.6 Transfer Control Instructions Table 5.3 Read/Write Instructions (Cont.) 5.6.1 First Dword Page Page Page Page Page 5.6.2 Second Dword 5.7 Memory Move Instructions 5.7.1 First Dword 5.7.2 Read/Write System Memory from SCRIPTS 5.7.3 Second Dword 5.7.4 Third Dword 5.8 Load and Store Instructions 5.8.1 First Dword 5.8.2 Second Dword Page Chapter 6 Electrical Specifications 6.1 DC Characteristics Table 6.1 Absolute Maximum Stress Ratings Table 6.2 Operating Conditions Table 6.3 Input Capacitance Table 6.4 Bidirectional SignalsMAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/ Table 6.5 Bidirectional SignalsGPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:4] Table 6.6 Bidirectional SignalsAD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/,STOP/,PERR/,PAR Table 6.7 Input SignalsCLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST,TMS, TRST/ Table 6.8 Output SignalTDO 6.2 TolerANT Technology Electrical Characteristics Table 6.11 TolerANT Technology Electrical Characteristics for SE SCSI Signals TolerANTTechnology Electrical Characteristics 6-7 Figure 6.1 Rise and Fall T ime Test Condition Figure 6.2 SCSI Input Filtering Figure 6.3 Hysteresis of SC SI Receivers 6-8 Electrical Specifications Figure 6.4 Input Current as a Function of Input Voltage Figure 6.5 Output Current as a Function of Output Voltage 6.3 AC Characteristics Figure 6.6 External Clock Table6.12 External Clock Tabl e 6.13 and Figure 6.7 provide Reset Input timing data. Figure 6.7 Reset Input Tabl e 6.14 and Figure 6.8 provide Interrupt Output timing data. Table 6.13 ResetInput Table 6.14 InterruptOutput 6.4 PCI and External Memory Interface Timing Diagrams Page PCI and External Memory InterfaceTiming Diagrams 6-13 6.4.1 Target Timing The tables and figures in this section describe target timings. Figure 6.9 PCI Configuration Register Read Table 6.15 PCIConfiguration Register Read Figure 6.10 PCI Configuration Register Write 6-14 Electrical Specifications Table 6.16 PCI Configuration Register Write Figure 6.11 32-Bit Operating Register/SCRIPTS RAMRead PCI and External Memory InterfaceTiming Diagrams 6-15 Table 6.17 32-Bit Operating Register/SCRIPTS RAM Read Figure 6.12 64-Bit Address Operating Register/SCRIPTSRAM Read 6-16 Electrical Specifications Table 6.18 64-Bit Address Operating Register/SCRIPTS RAM Read Figure 6.13 32-Bit Operating Register/SCRIPTS RAMWrite PCI and External Memory InterfaceTiming Diagrams 6-17 Table 6.19 32-Bit Operating Register/SCRIPTS RAM Write Figure 6.14 64-Bit Address Operating Register/SCRIPTS RAM Write 6-18 Electrical Specifications Table 6.20 64-Bit Address Operating Register/SCRIPTS RAM Write 6.4.2 Initiator Timing 6-20 Electrical Specifications Figure 6.15 Nonburst Opcode Fetch, 32-Bit Addressand Data Table 6.22 Burst Opcode Fetch, 32-Bit Address and Data 6-22 Electrical Specifications Figure 6.16 Burst Opcode Fetch, 32-Bit Addressand Data Table 6.23 Back-to-Back Read, 32-Bit Address and Data 6-24 Electrical Specifications Figure 6.17 Back-to-Back Read, 32-Bit Address and Data Table6.24 Back-to-BackWrite, 32-Bit Address and Data 6-26 Electrical Specifications Figure6.18 Back-to-BackWrite, 32-Bit Address and Data Page 6-28 Electrical Specifications Figure 6.19 Burst Read, 32-Bit A ddress and Data In Table 6.26 Burst Read, 64-Bit Address and Data 6-30 Electrical Specifications Figure 6.20 Burst Read, 64-Bit A ddress and Data In Table 6.27 Burst Write, 32-Bit Address and Data 6-32 Electrical Specifications Figure 6.21 Burst Write, 32-Bit Address and Data Table6.28 Burst Write, 64-BitAddress and 32-Bit Data 6-34 Electrical Specifications Figure 6.22 Burst Write, 64-Bit Address and 32-Bit Data 6.4.3 External Memory Timing 6-36 Electrical Specifications Figure 6.23 External Memory Read PCI and External Memory InterfaceTiming Diagrams 6-37 Figure 6.23 External Memory Read (Cont.) Table6.30 External Memory Write Page 6-40 Electrical Specifications Figure 6.24 External Memory Write PCI and External Memory InterfaceTiming Diagrams 6-41 Figure 6.24 External Memory Write (Cont.) Figure 6.25 Normal/Fast Memory (=128 Kbytes) Single Byte Access Read Cycle Table 6.31 Normal/Fast Memory (=128 Kbytes) Single Byte Access Read Cycle Figure 6.26 Normal/Fast Memory (=128 Kbytes) Single Byte Access Write Cycle Table 6.32 Normal/Fast Memory (=128 Kbytes) Single Byte Access Write Cycle 6-44 Electrical Specifications Figure 6.27 Normal/Fast Memory (=128 Kbytes) Multiple Byte Access R ead Cycle PCI and External Memory InterfaceTiming Diagrams 6-45 Figure 6.27 Normal/Fast Memory (=128 Kbytes) Multiple Byte Access R ead Cycle (Cont.) 6-46 Electrical Specifications Figure 6.28 Normal/Fast Memory (=128 Kbytes) Multiple Byte Access W rite Cycle PCI and External Memory InterfaceTiming Diagrams 6-47 Figure 6.28 Normal/Fast Memory (=128 Kbytes) Multiple Byte Access W rite Cycle (Cont.) Figure 6.29 Slow Memory (=128 Kbytes) Read Cycle 6-48 Electrical Specifications Table 6.33 Slow Memory (=128 Kbytes) Read Cycle Figure 6.30 Slow Memory (=128 Kbytes) Write Cycle Table 6.34 Slow Memory (128 Kbytes) Write Cycle Figure 6.31 64 Kbytes ROM Read Cycle 6-50 Electrical Specifications Table 6 .35 =64 Kbytes ROM Read Cycle Figure 6.32 64 Kbyte ROM Write Cycle Table 6 .36 =64 Kbyte ROM Write Cycle 6.5 SCSI Timing Diagrams The tables and diagrams in this section describe the LSI53C875A SCSI timings. Figure 6.33 Initiator Asynchronous Send Table 6.37 Initiator Asynchronous Send Figure 6.34 Initiator Asynchronous Receive Table 6.38 Initiator Asynchronous Receive Figure 6.35 Target Asynchronous Send Table 6.39 Target AsynchronousSend Figure 6.36 Target Asynchronous Receive Table 6.40 Target AsynchronousReceive Table 6.41 SCSI-1 Transfers (5.0 Mbytes) Page SCSI Timing Diagrams 6-57 Figure 6.37 Initiator and Target Synchronous Transfer Page Page Table6.44 160 PQFP Pin List by Location Page Table6.45 169 BGA Pin List by Location Appendix A Register Summary TableA.1 LSI53C875A PCI Register Map TableA.2 LSI53C875A SCSI Register Map TableA.1 LSI53C875A PCI Register Map (Cont.) Page TableA.2 LSI5 3C875A SCSI Register Map (Cont.) TableA.2 LSI53C875A SCSI Regis ter Map (Cont.) Page LSI53C875A PCI to Ultra SCSI Controller B-1 Appendix B External Memory Interface Diagram Examples B-2 External Memory Interface Diagram Examples Figure B.2 64 Kbyte Interface with 150 ns Memory External Memory Interface Diagram Examples B-3 Figure B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 ns Memory B-4 External Memory Interface Diagram Examples Figure B.4 512 Kbyte Interface with 150 ns Memory LSI53C875A PCI to Ultra SCSI Controller IX-1 Index Symbols IX-2 Index Index IX-3 Numerics A B IX-4 Index C D Index IX-5 E F G H I J L M Index IX-7 N O P R IX-8 Index S Index IX-9 T U IX-10 Index V W Customer Feedback Page U.S. Distributors by State U.S. Distributors by State (Continued) Direct Sales Representativesby State (Component and HAB) Sales Offices and Design Resource Centers Sales Offices and Design Resource Centers (Continued) International Distributors