LSI 53C875A technical manual Enabling Cache Mode, Issuing Cache Commands

software enabled or disabled to allow the user full flexibility in using these commands.

2.1.3.1 Enabling Cache Mode

In order to enable the cache logic to issue PCI cache commands (Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate) on any given PCI master operation the following conditions must be met:

•The Cache Line Size Enable bit in the DMA Control (DCNTL) register must be set.

•The PCI Cache Line Size register must contain a valid binary cache size, i.e. 2, 4, 8, 16, 32, 64, or 128 Dwords. Only these values are considered valid cache sizes.

•The programmed burst size (in Dwords) must be equal to or greater than the Cache Line Size register. The DMA Mode (DMODE) register bits [7:6] and Chip Test Five (CTEST5) bit 2 are the burst length bits.

•The part must be doing a PCI Master transfer. The following PCI Master transactions do not utilize the PCI cache logic and thus no PCI cache command is issued during these types of cycles: a nonprefetch SCRIPTS fetch, a Load/Store data transfer, or a data flush operation. All other types of PCI Master transactions will utilize the PCI cache logic.

The above conditions must be met for the cache logic to control the type of PCI cache command that is issued, along with any alignment that may be necessary during write operations. If these conditions are not met for any given PCI Master transaction, a Memory Read or Memory Write is issued and no cache write alignment is done.

2.1.3.2 Issuing Cache Commands

In order to issue each type of PCI cache command, the corresponding enable bit must be set (2 bits in the case of Memory Write and Invalidate). These bits are detailed below:

•To issue Memory Read Line commands, the Read Line enable bit in the DMA Mode (DMODE) register must be set.

2-10 Functional Description