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LSI 53C875A technical manual Target Asynchronous Send

Models: 53C875A

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Table 6.39 Target Asynchronous Send

Symbol	Parameter	Min	Max	Unit

t1	SREQ/ deasserted from SACK/ asserted	5	–	ns

t2	SREQ/ asserted from SACK/ deasserted	5	–	ns
t3	Data setup to SREQ/ asserted	55	–	ns
t4	Data hold from SACK/ asserted	0	–	ns

Figure 6.35 Target Asynchronous Send
SREQ/	n		n + 1
	t1	t2
SACK/		n	n + 1
	t3	t4
SD[15:0]/,	Valid n		Valid n + 1
SDP[1:0]/	Valid n		Valid n + 1
SDP[1:0]/

6-54	Electrical Specifications

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LSI 53C875A technical manual Target Asynchronous Send

Contents

Technical Manual C e m b e r 2 0 0Trademark Acknowledgment Audience OrganizationAnsi PCI Special Interest Group Conventions Used in This ManualRevision Record Revision Date RemarksViPreface Contents Chapter Signal Descriptions Chapter Registers Figures Contents Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR XivContents Chapter General Description Typical LSI53C875A System Application New Features in the LSI53C875A Benefits of Ultra ScsiTolerANT Technology LSI53C875A Benefits SummaryScsi Performance Integration PCI PerformanceEase of Use Flexibility Scripts RAMReliability TestabilityChapter Functional Description PCI Functional Description PCI AddressingPCI Bus Commands and Functions Supported Configuration SpacePCI Bus Commands and Encoding Types for the LSI53C875A Interrupt Acknowledge CommandSpecial Cycle Command CBE30 Command Type Supported as Master Supported as Slave2.3 I/O Read Command 2.4 I/O Write CommandReserved Command Memory Read CommandDual Address Cycle DAC Command Memory Read Multiple CommandMemory Read Line Command PCI Functional Description Memory Write and Invalidate Command PCI Cache Mode Enabling Cache Mode Issuing Cache CommandsMemory Read Caching Memory Write CachingPCI Cache Mode Alignment Host MemoryExamples Read ExampleWrite Example Write Example Scsi Functional Description Memory-to-Memory MovesPhase Mismatch Handling in Scripts Scripts ProcessorInternal Scripts RAM 3 64-Bit Addressing in Scripts Hardware Control of Scsi Activity LEDUsing the Scsi Clock Quadrupler Designing an Ultra Scsi SystemPrefetching Scripts Instructions Opcode Fetch Burst Capability Load and Store InstructionsJtag Boundary Scan Testing Scsi Loopback ModeParity Options Bits Used for Parity Control and Generation Bit Name Location DescriptionScsi Parity Errors and Interrupts Scsi Parity ControlDMA Fifo Parity Checking/GenerationDMA Fifo Sections Data PathsLSI53C875A Host Interface Scsi Data Paths Asynchronous Scsi SendSynchronous Scsi Send Asynchronous Scsi Receive Synchronous Scsi ReceiveScsi Bus Interface Scsi TerminationSelect/Reselect During Selection/Reselection Regulated Termination for Ultra ScsiSynchronous Operation Determining the Data Transfer RateDetermining the Synchronous Transfer Rate Scsi Control Three SCNTL3 Register, Bits 64 SCF20 Scsi Control Three SCNTL3 Register, Bits 20 CCF20Scsi Transfer Sxfer Register, Bits 75 TP20 Ultra Scsi Synchronous Data TransfersPolling and Hardware Interrupts Interrupt HandlingRegisters Functional Description Fatal vs. Nonfatal Interrupts Masking Stacked Interrupts Halting in an Orderly Fashion Sample Interrupt Service Routine Read Interrupt Status Zero ISTAT0Chained Block Moves Block Move and Chained Block Move Instructions Wide Scsi Send BitSwide Register Wide Scsi Receive BitSodl Register Chained Block Move Scripts Instruction Parallel ROM Interface Parallel ROM Support MAD31 Available Memory SpaceDefault Download Mode Serial Eeprom InterfacePower Management No Download ModeMode a Serial Eeprom Data Format Byte Name DescriptionPower State D0 Power State D1Power States Configuration Register BitsPower State D2 Power State D3Functional Description Chapter Signal Descriptions LSI53C875A Functional Signal Grouping LSI53C875A Functional Signal GroupingSignal Descriptions Internal Pull-ups on LSI53C875A SignalsSignal Name Pull-up Current Conditions for Pull-up LSI53C875A Internal Pull-upsPCI Bus Interface Signals System SignalsSystem Signals Type Strength DescriptionAddress and Data Signals Address and Data SignalsBus Command and Byte Enables are Interface Control Signals Interface Control SignalsInitialization Device Select is used as a chip select Arbitration Signals Error Reporting SignalsArbitration Signals Error Reporting SignalsScsi Bus Interface Signals Interrupt SignalScsi Bus Interface Signal Interrupt SignalScsi Signals Scsi Control SignalsScsi Signals 10 Scsi Control SignalsGpio Signals 11 Gpio SignalsScsi General Purpose I/O pin. Optionally Scsi General Purpose I/O pin. This pinROM Flash and Memory Interface Signals 12 ROM Flash and Memory Interface Signals13 Test Interface Signals Test Interface SignalsMemory Address/Data Bus. This bus is used Power and Ground Signals 14 Power and Ground Signals15 Decode of MAD Pins MAD Bus ProgrammingMAD Bus Programming Signal Descriptions PCI Configuration Registers Chapter RegistersVendor ID Read Only RegistersVIDVendor ID150 Command Read/Write Enable Parity Error ResponseDevice ID Read Only DIDDevice ID150WIE EBMEMS EISDPE SSERMA RTARegister DPRRevision ID Rev ID Read Only RIDRevision ID70Registers 0x09-0x0B Register 0x0CRegister 0x0E Register 0x0DRegister 0x0F BAR0 BAR1Registers 0x18-0x1B Registers 0x1C-0x27Registers 0x28-0x2B Registers 0x2C-0x2DRegisters 0x2E-0x2F Subsystem ID Read OnlySID Subsystem ID 150Erba Expansion ROM Base Address Read/WriteExpansion ROM Base Address 310 Registers 0x35-0x3B Register 0x3CCapabilities Pointer Read Only CPCapabilities Pointer70 Interrupt Line Read/Write ILInterrupt Line70Register 0x3D Register 0x3ERegister 0x3F MGMINGNT70Pmes D2S D1SDSI APSDscl DsltPEN Bridge Support Extensions Pmcsrbse Read OnlyData Read Only Scsi RegistersDATAData70 Scsi Register Address Map ARB10 Arbitration Mode Bits 1 Arbitration ModeScsi Control Zero SCNTL0 Read/Write Simple ArbitrationFull Arbitration, Selection/Reselection Start Start Sequence5EPC WatnAAP ADB EXCDHP CON RSTAesp IarbSSTStart Scsi Transfer0 Chained Mode Scsi Control Two SCNTL2 Read/WriteSDU Scsi Disconnect UnexpectedSlpmd SlphbenWSS VUE0Ultra Scsi Enable WSRWide Scsi Receive0Scsi Control Three SCNTL3 Read/Write USEEnable Wide Scsi SCF20 Synchronous Clock Conversion FactorEWS CCF20 Clock Conversion FactorSRE RREENC Scsi Transfer Sxfer Read/Write TP20 Scsi Synchronous Transfer PeriodTransfer Rate Synch CLK MHzBits Period ns Mbytes/s MO40 Max Scsi Synchronous Offset Maximum Synchronous Offset Synchronous OffsetScsi Destination ID Sdid Read/Write Encoded Destination Scsi IDGeneral Purpose GPREG0 Read/Write GpioScsi First Byte Received Sfbr Read/Write Sfbr Scsi First Byte Received70REQ ACKBSY SELRegister 0x0A Register 0x0BVAL EnidSREQ/ Status SACK/ StatusSBSY/ Status SSEL/ StatusMdpe AbrtSSI SIRScsi Registers ORF ILFOLF LOA AIPWOA Bytes or Words Scsi Synchronous Data Fifo Word CountSSTAT2 bit SDP0L ORF1 ILF1OLF1 SPL1 LdscSDP1 DSAInterrupt Status Zero ISTAT0 Read/Write Srst Software Reset6Abort Operation Signal Process SigpSEM SemaphoreSipscsi Interrupt Pending1 Dipdma Interrupt Pending0Srun FlshSyncirqd Mailbox Zero MBOX0 Read/Write MBOX0 Mailbox Zero70Mailbox One MBOX1 Read/Write MBOX1 Mailbox One70Chip Test Zero CTEST0 Read/Write FMTByte Empty in DMA FIFO70Chip Test One CTEST1 Read Only FFLByte Full in DMA FIFO70Ddir Register 0x1ACIO Dreq TeopDack FLF Register 0x1BCLF Temp Registers 0x1C-0x1FDMA Fifo Dfifo 58Registers Bdis FBL3ZSD SrtmFBL20 Fifo Byte Control Chip Test Five CTEST5 Read/WriteAdck Clock Address IncrementorBbck DFSMasr BL2Dfdma FIFO70 DBCDMA Command Dcmd Read/Write Dcmd DMA Command70Dnad Registers 0x2C-0x2FDSP DMA Scripts Pointer Save Dsps Read/Write Dsps DMA Scripts Pointer Save310Scratch Register a Scratcha Read/Write Scratcha Scratch Register a 310DMA Mode Dmode Read/Write BL10 Burst LengthSource I/O Memory Enable Destination I/O Memory EnableERLEnable Read Line3 SiomEnable Read Multiple Burst Opcode Fetch EnableErmp BOFDMA Interrupt Enable Dien Read/Write Master Data Parity Error Bus FaultScripts Interrupt Instruction Received Reserved Illegal Instruction DetectedRegister 0x3A Register 0x3BClse PFFSSM Single Step ModeIrqmirq Mode3 IRQ Disable STDStart DMA Operation2Irqd COMLSI53C700 Compatibility00x40 Registers 0x3C-0x3FAdder CMP RSLSGE UDCSTO GENInitiator Mode Phase Mismatch Target Mode SATN/ Active HTHHandshake-to-Handshake Timer Expired0Scsi Interrupt Status Zero SIST0 Read Only This bit is set when an arbitration only or full arbitration Parity Error Scsi RST/ ReceivedPAR Scsi Interrupt Status One SIST1 Read OnlyHandshake-to-Handshake Timer Expired HTHScsi Longitudinal Parity Slpar Read/Write Slpar Scsi Longitudinal Parity70Data Bytes Running Slpar Memory Access Control Macntl Read/Write Scsi Wide Residue Swide Read/WriteSwide Scsi Wide Residue70 TYPDWR DRDPscpt Scpts ScriptsGpio Enable Gpiogpio Enable10Scsi Timer Zero STIME0 Read/Write HTH30 Handshake-to-HandshakeTimer PeriodSEL30 Selection Time-Out30 Gensf HthbaHthsf Register 0x4A Register 0x4BRegister 0x4C SsaidSLT ARTRegister 0x4D SclkISO QENRegister 0x4E QselSCE ROFSZM AWSEXT LOWRegister 0x4F STRDisable Single Initiator Response Timer Test ModeS16 Bit System TTMScsi Input Data Latch Sidl Read Only STWSidlscsi Input Data Latch150 Register 0x53 LockEnable Phase Mismatch Jump Chip Control 0 CCNTL0 Read/WriteEnpmj Pmjctl Jump Control6Disfc EnndjDils Ddac Zmode64TIMOD Enable 64-Bit Direct Bmov EN64TIBMVEN64DBMV Scsi Bus Data Lines Sbdl Read Only64-Bit Scripts Selectors Register 0x5A-0x5BRegisters 0x5C-0x5F Registers 0x60-0x9FRegisters 0xA0-0xA3 Memory Move Read Selector Mmrs Read/WriteMmrs Memory Move Read Selector MmrsRegisters 0xA4-0xA7 Registers 0xA8-0xABMmws SFSRegisters 0xAC-0xAF Registers 0xB0-0xB3DRS SbmsPhase Mismatch Jump Registers Registers 0xB4-0xB7Registers 0xB8-0xBB Registers 0xBC-0xBFRegisters 0xC0-0xC3 Registers 0xC4-0xC7PMJAD1 PMJAD2Registers 0xCC-0xCF Registers 0xC8-0xCBRBC Registers 0xD0-0xD3 Entry Storage Address ESA Read/WriteESA Entry Storage Address 310Registers 0xD8-0xDA Registers 0xD4-0xD7SBC Register 0xDB Registers 0xDC-0xDFRegisters 0xE0-0xFF CsbcLow Level Register Interface Mode Scsi ScriptsHigh Level Scsi Scripts Mode Scripts Instructions Sample OperationInstruction Description Scsi Scripts Instruction Set Scripts Overview Block Move Instruction First DwordTIA Direct AddressingTable Indirect Bit Addressing Command Not Used Don’t Care OPCOpCode27 Target ModeOPC Instruction Defined Initiator Mode SCSIP20 Scsi Phase2624 Scsi Phase Scsi Information Transfer PhaseTC230 Transfer Counter230 Target Mode Initiator Mode I/O InstructionSecond Dword Start Address 310IT10 Instruction Type I/O Instruction 3130 OPC20 OpCode 2927Reselect Instruction Instruction DefinedDisconnect Instruction Wait Select InstructionSet Instruction Clear InstructionSelect Instruction Wait Disconnect Instruction Wait Reselect InstructionRelative Addressing Mode TITable Indirect Mode25Direct Table IndirectRelative BitCommand Table Offset Absolute Jump Offset Table RelativeSet/Clear Sack Reserved Set/Clear SatnRead/Write Instructions IT10 Instruction Type Read/Write Instruction 3130O20 Operator 2624 Use data8/SFBRRead-Modify-Write Cycles A60 Register Address A60 2216Move To/From Sfbr Cycles Read/Write InstructionsTransfer Control Instructions Transfer Control Instructions IT10 Instruction Type Transfer Control 3130Jump Instruction Call Instruction Return InstructionInterrupt Instruction Interrupt-on-the-Fly InstructionScsi Phase Comparisons RARelative Addressing Mode23Jump/Call an Absolute Address Jump/Call a Relative AddressJMP Bit 2 is assertedJump If True/False Compare Phase Wait for Valid PhaseCompare Data WVPMemory Move Instructions DCVData Compare Value Jump Address 310Reserved 2825 IT20 Instruction Type Memory Move 3129No Flush Read/Write System Memory from Scripts Dsps Register 310Load and Store Instructions Third DwordTemp Register 310 Bit A1 Bit A0 Number of Bytes Allowed to Load and StoreIT20 Instruction Type 3129 DSA RelativeReserved 2726 No Flush Store instruction only Bit Source DestinationThis bit has no effect unless the Prefetch Enable bit DMA Control Dcntl register is setScsi Scripts Instruction Set Chapter Electrical Specifications DC CharacteristicsSymbol Parameter Min Max Unit Test Conditions Absolute Maximum Stress Ratings1Operating Conditions1 Input CapacitanceBidirectional Signals-MAD70, MAS/10, MCE/, MOE/, MWE Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER/, GPIO24Output Signal-TDO Output Signals-IRQ/, MAC/TESTOUT, REQ TolerANT Technology Electrical CharacteristicsOutput Signal-SERR Symbol Parameter Min1 Max Unit Test Conditions PqfpRise and Fall Time Test Condition Input Current as a Function of Input Voltage Symbol Parameter Min Max Unit AC Characteristics12 External Clock1 Reset Input Interrupt OutputPCI and External Memory Interface Timing Diagrams Electrical Specifications PCI Configuration Register Read 15 PCI Configuration Register ReadTarget Timing 16 PCI Configuration Register Write 10 PCI Configuration Register Write17 32-Bit Operating Register/SCRIPTS RAM Read 11 32-Bit Operating Register/SCRIPTS RAM Read18 64-Bit Address Operating Register/SCRIPTS RAM Read 12 64-Bit Address Operating Register/SCRIPTS RAM Read19 32-Bit Operating Register/SCRIPTS RAM Write 13 32-Bit Operating Register/SCRIPTS RAM Write20 64-Bit Address Operating Register/SCRIPTS RAM Write 14 64-Bit Address Operating Register/SCRIPTS RAM WriteInitiator Timing 21 Nonburst Opcode Fetch, 32-Bit Address and Data15 Nonburst Opcode Fetch, 32-Bit Address and Data 22 Burst Opcode Fetch, 32-Bit Address and Data 16 Burst Opcode Fetch, 32-Bit Address and Data 23 Back-to-Back Read, 32-Bit Address and Data 17 Back-to-Back Read, 32-Bit Address and Data 24 Back-to-Back Write, 32-Bit Address and Data 18 Back-to-Back Write, 32-Bit Address and Data 25 Burst Read, 32-Bit Address and Data 19 Burst Read, 32-Bit Address and Data 26 Burst Read, 64-Bit Address and Data 20 Burst Read, 64-Bit Address and Data 27 Burst Write, 32-Bit Address and Data 21 Burst Write, 32-Bit Address and Data 28 Burst Write, 64-Bit Address and 32-Bit Data 22 Burst Write, 64-Bit Address and 32-Bit Data External Memory Timing 29 External Memory Read23 External Memory Read STOP/ Driven by LSI53C875A 30 External Memory Write External Memory Write timings start on 24 External Memory Write Data Byte Enable Address out from MOE/, MCE/ High Driven by LSI53C875A Higher Valid Write Data CBE30 Byte Enable Data Byte Enable Out Lower Address Data LSI53C875A-Data Data Byte Enable Data Out Symbol Parameter Min Slow Memory ≤ 128 Kbytes Read CycleSlow Memory ≤ 128 Kbytes Write Cycle 30 Slow Memory ≤ 128 Kbytes Write Cycle≤ 64 Kbytes ROM Read Cycle ≤ 64 Kbyte ROM Write Cycle 32 ≤ 64 Kbyte ROM Write CycleScsi Timing Diagrams 37 Initiator Asynchronous Send38 Initiator Asynchronous Receive 34 Initiator Asynchronous Receive39 Target Asynchronous Send 35 Target Asynchronous Send40 Target Asynchronous Receive 41 SCSI-1 Transfers 5.0 MbytesSymbol Parameter Min Max Unit 37 Initiator and Target Synchronous Transfer Package Diagrams 38 LSI53C875A 160-Pin Pqfp Mechanical DrawingPin Pqfp P3 Mechanical Drawing Sheet 2 Signal Pin 44 160 Pqfp Pin List by LocationPin BGA Mechanical Drawing 45 169 BGA Pin List by Location NC1Appendix a Register Summary Table A.2 LSI53C875A Scsi Register Map Register Summary Scratch Registers C-RSCRATCHC-SCRATCHR Table A.2 LSI53C875A Scsi Register Map Register Summary Appendix B External Memory Interface Diagram Examples Figure B.2 64 Kbyte Interface with 150 ns Memory External Memory Interface Diagram Examples Figure B.4 512 Kbyte Interface with 150 ns Memory Symbols IndexIX-2Index Numerics SGE 4-74,4-77 SIIX-4Index IX-5 IX-6Index IX-7 IX-8Index IX-9 IX-10Index Customer Feedback Reader’s Comments Excellent Good Average Fair PoorDistributors by State CaliforniaNew York Direct Sales Representatives by State Component and HAB Sales Offices and Design Resource Centers North AmericaKorea International Distributors Australia Hong Kong