Target Timing, PCI Configuration Register Read | LSI 53C875A

6.4.1 Target Timing

The tables and figures in this section describe target timings.

Table 6.15 PCI Configuration Register Read

Symbol	Parameter	Min	Max	Unit

t1	Shared signal input setup time	7	–	ns

t2	Shared signal input hold time	0	–	ns
t3	CLK to shared signal output valid	–	11	ns

Figure 6.9	PCI Configuration Register Read

CLK (Driven by System)

FRAME/ (Driven by System)

AD (Driven by Master-Addr; LSI53C875A-Data)

C_BE/ (Driven by Master)

PAR (Driven by Master-Addr; LSI53C875A-Data)

IRDY/ (Driven by Master)

TRDY/ (Driven by LSI53C875A)

STOP/ (Driven by LSI53C875A)

DEVSEL/

(Driven by LSI53C875A)

IDSEL (Driven by Master)

t1

t2

t3

t1

Addr

Data Out

In

t2

t2

t1

CMD

Byte Enable

t2

t1

t3

In

Out

t2

t2

t1

t3

t1					t3
t1					t3

t2

PCI and External Memory Interface Timing Diagrams

6-13

Image 251

LSI 53C875A technical manual Target Timing, PCI Configuration Register Read

Contents

C e m b e r 2 0 0 Technical Manual Trademark Acknowledgment Organization Audience Ansi Revision Date Remarks PCI Special Interest GroupConventions Used in This Manual Revision Record ViPreface Contents Chapter Signal Descriptions Chapter Registers Figures Contents Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR XivContents Chapter General Description Typical LSI53C875A System Application Benefits of Ultra Scsi New Features in the LSI53C875A LSI53C875A Benefits Summary TolerANT Technology Scsi Performance Ease of Use PCI PerformanceIntegration Scripts RAM Flexibility Testability Reliability Chapter Functional Description PCI Addressing PCI Functional Description Configuration Space PCI Bus Commands and Functions Supported CBE30 Command Type Supported as Master Supported as Slave PCI Bus Commands and Encoding Types for the LSI53C875AInterrupt Acknowledge Command Special Cycle Command Memory Read Command 2.3 I/O Read Command2.4 I/O Write Command Reserved Command Memory Read Line Command Memory Read Multiple CommandDual Address Cycle DAC Command PCI Functional Description Memory Write and Invalidate Command PCI Cache Mode Issuing Cache Commands Enabling Cache Mode Memory Write Caching Memory Read Caching Host Memory PCI Cache Mode Alignment Read Example Examples Write Example Write Example Memory-to-Memory Moves Scsi Functional Description Scripts Processor Phase Mismatch Handling in Scripts Internal Scripts RAM Hardware Control of Scsi Activity LED 3 64-Bit Addressing in Scripts Designing an Ultra Scsi System Using the Scsi Clock Quadrupler Prefetching Scripts Instructions Load and Store Instructions Opcode Fetch Burst Capability Scsi Loopback Mode Jtag Boundary Scan Testing Parity Options Bit Name Location Description Bits Used for Parity Control and Generation Scsi Parity Control Scsi Parity Errors and Interrupts Parity Checking/Generation DMA Fifo Data Paths DMA Fifo Sections Asynchronous Scsi Send LSI53C875A Host Interface Scsi Data Paths Synchronous Scsi Send Synchronous Scsi Receive Asynchronous Scsi Receive Scsi Termination Scsi Bus Interface Regulated Termination for Ultra Scsi Select/Reselect During Selection/Reselection Determining the Data Transfer Rate Synchronous Operation Determining the Synchronous Transfer Rate Ultra Scsi Synchronous Data Transfers Scsi Control Three SCNTL3 Register, Bits 64 SCF20Scsi Control Three SCNTL3 Register, Bits 20 CCF20 Scsi Transfer Sxfer Register, Bits 75 TP20 Registers Interrupt HandlingPolling and Hardware Interrupts Functional Description Fatal vs. Nonfatal Interrupts Masking Stacked Interrupts Halting in an Orderly Fashion Read Interrupt Status Zero ISTAT0 Sample Interrupt Service Routine Chained Block Moves Wide Scsi Send Bit Block Move and Chained Block Move Instructions Sodl Register Wide Scsi Receive BitSwide Register Chained Block Move Scripts Instruction Parallel ROM Interface MAD31 Available Memory Space Parallel ROM Support Serial Eeprom Interface Default Download Mode Byte Name Description Power ManagementNo Download Mode Mode a Serial Eeprom Data Format Configuration Register Bits Power State D0Power State D1 Power States Power State D3 Power State D2 Functional Description Chapter Signal Descriptions LSI53C875A Functional Signal Grouping LSI53C875A Functional Signal Grouping LSI53C875A Internal Pull-ups Signal DescriptionsInternal Pull-ups on LSI53C875A Signals Signal Name Pull-up Current Conditions for Pull-up Type Strength Description PCI Bus Interface SignalsSystem Signals System Signals Bus Command and Byte Enables are Address and Data SignalsAddress and Data Signals Initialization Device Select is used as a chip select Interface Control SignalsInterface Control Signals Error Reporting Signals Arbitration SignalsError Reporting Signals Arbitration Signals Interrupt Signal Scsi Bus Interface SignalsInterrupt Signal Scsi Bus Interface Signal 10 Scsi Control Signals Scsi SignalsScsi Control Signals Scsi Signals Scsi General Purpose I/O pin. This pin Gpio Signals11 Gpio Signals Scsi General Purpose I/O pin. Optionally 12 ROM Flash and Memory Interface Signals ROM Flash and Memory Interface Signals Memory Address/Data Bus. This bus is used Test Interface Signals13 Test Interface Signals 14 Power and Ground Signals Power and Ground Signals MAD Bus Programming 15 Decode of MAD Pins MAD Bus Programming Signal Descriptions Chapter Registers PCI Configuration Registers VIDVendor ID150 RegistersVendor ID Read Only DIDDevice ID150 Command Read/WriteEnable Parity Error Response Device ID Read Only EIS WIEEBM EMS RTA DPESSE RMA RIDRevision ID70 RegisterDPR Revision ID Rev ID Read Only Register 0x0C Registers 0x09-0x0B Register 0x0F Register 0x0DRegister 0x0E BAR1 BAR0 Registers 0x2C-0x2D Registers 0x18-0x1BRegisters 0x1C-0x27 Registers 0x28-0x2B Subsystem ID 150 Registers 0x2E-0x2FSubsystem ID Read Only SID Expansion ROM Base Address 310 Expansion ROM Base Address Read/WriteErba Interrupt Line Read/Write ILInterrupt Line70 Registers 0x35-0x3BRegister 0x3C Capabilities Pointer Read Only CPCapabilities Pointer70 MGMINGNT70 Register 0x3DRegister 0x3E Register 0x3F Pmes APS D2SD1S DSI Bridge Support Extensions Pmcsrbse Read Only DsclDslt PEN DATAData70 Scsi RegistersData Read Only Scsi Register Address Map Simple Arbitration ARB10 Arbitration Mode Bits 1Arbitration Mode Scsi Control Zero SCNTL0 Read/Write Start Start Sequence5 Full Arbitration, Selection/Reselection AAP WatnEPC DHP EXCADB Iarb CONRST Aesp SSTStart Scsi Transfer0 Scsi Disconnect Unexpected Chained ModeScsi Control Two SCNTL2 Read/Write SDU VUE0 SlpmdSlphben WSS USE Ultra Scsi EnableWSRWide Scsi Receive0 Scsi Control Three SCNTL3 Read/Write CCF20 Clock Conversion Factor Enable Wide ScsiSCF20 Synchronous Clock Conversion Factor EWS ENC RRESRE TP20 Scsi Synchronous Transfer Period Scsi Transfer Sxfer Read/Write Bits Period ns Mbytes/s Synch CLK MHzTransfer Rate MO40 Max Scsi Synchronous Offset Synchronous Offset Maximum Synchronous Offset Gpio Scsi Destination ID Sdid Read/WriteEncoded Destination Scsi ID General Purpose GPREG0 Read/Write Sfbr Scsi First Byte Received70 Scsi First Byte Received Sfbr Read/Write SEL REQACK BSY Enid Register 0x0ARegister 0x0B VAL SSEL/ Status SREQ/ StatusSACK/ Status SBSY/ Status SIR MdpeAbrt SSI Scsi Registers OLF ILFORF WOA AIPLOA SSTAT2 bit Scsi Synchronous Data Fifo Word CountBytes or Words SDP0L OLF1 ILF1ORF1 DSA SPL1Ldsc SDP1 Abort Operation Srst Software Reset6Interrupt Status Zero ISTAT0 Read/Write Semaphore Signal ProcessSigp SEM Dipdma Interrupt Pending0 Sipscsi Interrupt Pending1 Syncirqd FlshSrun MBOX1 Mailbox One70 Mailbox Zero MBOX0 Read/WriteMBOX0 Mailbox Zero70 Mailbox One MBOX1 Read/Write FFLByte Full in DMA FIFO70 Chip Test Zero CTEST0 Read/WriteFMTByte Empty in DMA FIFO70 Chip Test One CTEST1 Read Only CIO Register 0x1ADdir Dack TeopDreq CLF Register 0x1BFLF DMA Fifo Dfifo Registers 0x1C-0x1FTemp 58Registers Srtm BdisFBL3 ZSD Clock Address Incrementor FBL20 Fifo Byte ControlChip Test Five CTEST5 Read/Write Adck BL2 BbckDFS Masr DBC Dfdma FIFO70 Dcmd DMA Command70 DMA Command Dcmd Read/Write DSP Registers 0x2C-0x2FDnad Scratcha Scratch Register a 310 DMA Scripts Pointer Save Dsps Read/WriteDsps DMA Scripts Pointer Save310 Scratch Register a Scratcha Read/Write BL10 Burst Length DMA Mode Dmode Read/Write Siom Source I/O Memory EnableDestination I/O Memory Enable ERLEnable Read Line3 BOF Enable Read MultipleBurst Opcode Fetch Enable Ermp Illegal Instruction Detected DMA Interrupt Enable Dien Read/WriteMaster Data Parity Error Bus Fault Scripts Interrupt Instruction Received Reserved PFF Register 0x3ARegister 0x3B Clse Irqmirq Mode3 Single Step ModeSSM COMLSI53C700 Compatibility0 IRQ DisableSTDStart DMA Operation2 Irqd Adder Registers 0x3C-0x3F0x40 UDC CMPRSL SGE GEN STO Scsi Interrupt Status Zero SIST0 Read Only HTHHandshake-to-Handshake Timer Expired0Initiator Mode Phase Mismatch Target Mode SATN/ Active This bit is set when an arbitration only or full arbitration Scsi Interrupt Status One SIST1 Read Only Parity ErrorScsi RST/ Received PAR Slpar Scsi Longitudinal Parity70 Handshake-to-Handshake Timer ExpiredHTH Scsi Longitudinal Parity Slpar Read/Write Data Bytes Running Slpar TYP Memory Access Control Macntl Read/WriteScsi Wide Residue Swide Read/Write Swide Scsi Wide Residue70 Scpts Scripts DWRDRD Pscpt HTH30 Handshake-to-HandshakeTimer Period Gpio EnableGpiogpio Enable10 Scsi Timer Zero STIME0 Read/Write SEL30 Selection Time-Out30 Hthsf HthbaGensf Register 0x4B Register 0x4A ART Register 0x4CSsaid SLT QEN Register 0x4DSclk ISO ROF Register 0x4EQsel SCE LOW SZMAWS EXT STR Register 0x4F TTM Disable Single Initiator ResponseTimer Test Mode S16 Bit System Sidlscsi Input Data Latch150 STWScsi Input Data Latch Sidl Read Only Lock Register 0x53 Pmjctl Jump Control6 Enable Phase Mismatch JumpChip Control 0 CCNTL0 Read/Write Enpmj Dils EnndjDisfc 64TIMOD ZmodeDdac Scsi Bus Data Lines Sbdl Read Only Enable 64-Bit Direct BmovEN64TIBMV EN64DBMV Registers 0x60-0x9F 64-Bit Scripts SelectorsRegister 0x5A-0x5B Registers 0x5C-0x5F Memory Move Read Selector Mmrs Registers 0xA0-0xA3Memory Move Read Selector Mmrs Read/Write Mmrs SFS Registers 0xA4-0xA7Registers 0xA8-0xAB Mmws Sbms Registers 0xAC-0xAFRegisters 0xB0-0xB3 DRS Registers 0xBC-0xBF Phase Mismatch Jump RegistersRegisters 0xB4-0xB7 Registers 0xB8-0xBB PMJAD2 Registers 0xC0-0xC3Registers 0xC4-0xC7 PMJAD1 RBC Registers 0xC8-0xCBRegisters 0xCC-0xCF Entry Storage Address 310 Registers 0xD0-0xD3Entry Storage Address ESA Read/Write ESA SBC Registers 0xD4-0xD7Registers 0xD8-0xDA Csbc Register 0xDBRegisters 0xDC-0xDF Registers 0xE0-0xFF Scsi Scripts Low Level Register Interface Mode High Level Scsi Scripts Mode Instruction Description Sample OperationScripts Instructions Scsi Scripts Instruction Set Scripts Overview First Dword Block Move Instruction Table Indirect Bit Addressing Direct AddressingTIA Command Not Used Don’t Care OPC Instruction Defined Target ModeOPCOpCode27 Initiator Mode SCSIP20 Scsi Phase2624 TC230 Transfer Counter230 Scsi Information Transfer PhaseScsi Phase Start Address 310 Target Mode Initiator ModeI/O Instruction Second Dword Instruction Defined IT10 Instruction Type I/O Instruction 3130OPC20 OpCode 2927 Reselect Instruction Clear Instruction Disconnect InstructionWait Select Instruction Set Instruction Select Instruction Wait Reselect Instruction Wait Disconnect Instruction TITable Indirect Mode25 Relative Addressing Mode Bit DirectTable Indirect Relative Table Relative Command Table Offset Absolute Jump Offset Set/Clear Satn Set/Clear Sack Reserved Use data8/SFBR Read/Write InstructionsIT10 Instruction Type Read/Write Instruction 3130 O20 Operator 2624 A60 Register Address A60 2216 Read-Modify-Write Cycles Read/Write Instructions Move To/From Sfbr Cycles Transfer Control Instructions Jump Instruction IT10 Instruction Type Transfer Control 3130Transfer Control Instructions Return Instruction Call Instruction Interrupt-on-the-Fly Instruction Interrupt Instruction Jump/Call a Relative Address Scsi Phase ComparisonsRARelative Addressing Mode23 Jump/Call an Absolute Address Jump If True/False Bit 2 is assertedJMP WVP Compare PhaseWait for Valid Phase Compare Data Jump Address 310 Memory Move InstructionsDCV Data Compare Value No Flush IT20 Instruction Type Memory Move 3129Reserved 2825 Dsps Register 310 Read/Write System Memory from Scripts Bit A1 Bit A0 Number of Bytes Allowed to Load and Store Load and Store InstructionsThird Dword Temp Register 310 Bit Source Destination IT20 Instruction Type 3129DSA Relative Reserved 2726 No Flush Store instruction only DMA Control Dcntl register is set This bit has no effect unless the Prefetch Enable bit Scsi Scripts Instruction Set DC Characteristics Chapter Electrical Specifications Input Capacitance Symbol Parameter Min Max Unit Test ConditionsAbsolute Maximum Stress Ratings1 Operating Conditions1 Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER/, GPIO24 Bidirectional Signals-MAD70, MAS/10, MCE/, MOE/, MWE Output Signal-TDO Output Signal-SERR TolerANT Technology Electrical CharacteristicsOutput Signals-IRQ/, MAC/TESTOUT, REQ Pqfp Symbol Parameter Min1 Max Unit Test Conditions Rise and Fall Time Test Condition Input Current as a Function of Input Voltage 12 External Clock1 AC CharacteristicsSymbol Parameter Min Max Unit Interrupt Output Reset Input PCI and External Memory Interface Timing Diagrams Electrical Specifications Target Timing 15 PCI Configuration Register ReadPCI Configuration Register Read 10 PCI Configuration Register Write 16 PCI Configuration Register Write 11 32-Bit Operating Register/SCRIPTS RAM Read 17 32-Bit Operating Register/SCRIPTS RAM Read 12 64-Bit Address Operating Register/SCRIPTS RAM Read 18 64-Bit Address Operating Register/SCRIPTS RAM Read 13 32-Bit Operating Register/SCRIPTS RAM Write 19 32-Bit Operating Register/SCRIPTS RAM Write 14 64-Bit Address Operating Register/SCRIPTS RAM Write 20 64-Bit Address Operating Register/SCRIPTS RAM Write 21 Nonburst Opcode Fetch, 32-Bit Address and Data Initiator Timing 15 Nonburst Opcode Fetch, 32-Bit Address and Data 22 Burst Opcode Fetch, 32-Bit Address and Data 16 Burst Opcode Fetch, 32-Bit Address and Data 23 Back-to-Back Read, 32-Bit Address and Data 17 Back-to-Back Read, 32-Bit Address and Data 24 Back-to-Back Write, 32-Bit Address and Data 18 Back-to-Back Write, 32-Bit Address and Data 25 Burst Read, 32-Bit Address and Data 19 Burst Read, 32-Bit Address and Data 26 Burst Read, 64-Bit Address and Data 20 Burst Read, 64-Bit Address and Data 27 Burst Write, 32-Bit Address and Data 21 Burst Write, 32-Bit Address and Data 28 Burst Write, 64-Bit Address and 32-Bit Data 22 Burst Write, 64-Bit Address and 32-Bit Data 29 External Memory Read External Memory Timing 23 External Memory Read STOP/ Driven by LSI53C875A 30 External Memory Write External Memory Write timings start on 24 External Memory Write Data Byte Enable Address out from MOE/, MCE/ High Driven by LSI53C875A Higher Valid Write Data CBE30 Byte Enable Data Byte Enable Out Lower Address Data LSI53C875A-Data Data Byte Enable Data Out Slow Memory ≤ 128 Kbytes Read Cycle Symbol Parameter Min 30 Slow Memory ≤ 128 Kbytes Write Cycle Slow Memory ≤ 128 Kbytes Write Cycle ≤ 64 Kbytes ROM Read Cycle 32 ≤ 64 Kbyte ROM Write Cycle ≤ 64 Kbyte ROM Write Cycle 37 Initiator Asynchronous Send Scsi Timing Diagrams 34 Initiator Asynchronous Receive 38 Initiator Asynchronous Receive 35 Target Asynchronous Send 39 Target Asynchronous Send 41 SCSI-1 Transfers 5.0 Mbytes 40 Target Asynchronous Receive Symbol Parameter Min Max Unit 37 Initiator and Target Synchronous Transfer 38 LSI53C875A 160-Pin Pqfp Mechanical Drawing Package Diagrams Pin Pqfp P3 Mechanical Drawing Sheet 2 44 160 Pqfp Pin List by Location Signal Pin Pin BGA Mechanical Drawing NC1 45 169 BGA Pin List by Location Appendix a Register Summary Table A.2 LSI53C875A Scsi Register Map Register Summary Scratch Registers C-RSCRATCHC-SCRATCHR Table A.2 LSI53C875A Scsi Register Map Register Summary Appendix B External Memory Interface Diagram Examples Figure B.2 64 Kbyte Interface with 150 ns Memory External Memory Interface Diagram Examples Figure B.4 512 Kbyte Interface with 150 ns Memory Index Symbols IX-2Index SGE 4-74,4-77 SI Numerics IX-4Index IX-5 IX-6Index IX-7 IX-8Index IX-9 IX-10Index Customer Feedback Excellent Good Average Fair Poor Reader’s Comments California Distributors by State New York Direct Sales Representatives by State Component and HAB North America Sales Offices and Design Resource Centers Korea Australia Hong Kong International Distributors