LSI 53C875A technical manual Power and Ground Signals

3.8 Power and Ground Signals

Table 3.14 describes the Power and Ground signals.

Table 3.14 Power and Ground Signals

Name	PQFP	BGA	Type	Strength	Description
VSS_I/O	4, 10, 14, 18,	A9, B11, D12,	G	N/A	Ground for PCI bus
	23, 27, 31, 37,	E13, F12,			drivers/receivers, SCSI bus
	42, 48, 69, 79,	G11, J13,			drivers/receivers, local memory
	88, 93, 99,	K10, K12, N9			interface drivers, and other I/O
	104, 109, 114,				pins.
	123, 133, 152,
	158
VDD_I/O	8, 21, 33, 45,	B10, C12, D2,	P	N/A	Power for PCI bus
	63, 74, 84,	D5, E8, G1,			drivers/receivers, SCSI bus
	118, 128, 138,	J5, J7, K1,			drivers/receivers, local memory
	155	L11, M10			interface drivers/receivers, and
					other I/O pins.
VDD_CORE	51, 83, 149	A5, L5, L12	P	N/A	Power for core logic.
VSS_CORE	55, 80, 146	C6, L6, N12	G	N/A	Ground for core logic.
VDDA	129	D9	P	N/A	Power for analog cells (clock
					quadrupler and diffsense logic).
VSSA	132	B9	G	N/A	Ground for analog cells (clock
					quadrupler and diffsense logic).
NC	72, 73, 75, 76,	A12, A13, B2,	N/A	N/A	These pins have NO internal
	78, 81, 82,	B3, B12, B13,			connection.
	119–122, 124,	C3, C8, C11,
	125, 134, 135	D1, D8, D10,
		E9, F4-6, G5,
		H4, H8, J3,
		K3, K9, M2,
		M4, M11-13,
		N2, N10, N11,
		N13

Note:

The I/O driver pad rows and digital core have isolated power supplies as indicated by the “I/O”

and “CORE” extensions on their respective V and V	DD	names. These power and ground pins
SS

should be connected directly to the primary power and ground planes of the circuit board. Bypass capacitors of 0.01 ∝ F should be applied between adjacent VSS and VDD pairs wherever possible. Do not connect bypass capacitors between VSS and VDD pairs that cross power and ground bus boundaries.

Power and Ground Signals 3-13