B.3

128

Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte

 

 

Interface with 150 ns Memory

B-3

B.4

512

Kbyte Interface with 150 ns Memory

B-4

Tables

2.1PCI Bus Commands and Encoding Types for the

 

LSI53C875A

2-4

2.2

PCI Cache Mode Alignment

2-12

2.3

Bits Used for Parity Control and Generation

2-25

2.4

SCSI Parity Control

2-26

2.5

SCSI Parity Errors and Interrupts

2-26

2.6

Parallel ROM Support

2-49

2.7

Mode A Serial EEPROM Data Format

2-51

2.8

Power States

2-52

3.1

LSI53C875A Internal Pull-ups

3-3

3.2

System Signals

3-4

3.3

Address and Data Signals

3-5

3.4

Interface Control Signals

3-6

3.5

Arbitration Signals

3-7

3.6

Error Reporting Signals

3-7

3.7

Interrupt Signal

3-8

3.8

SCSI Bus Interface Signal

3-8

3.9

SCSI Signals

3-9

3.10

SCSI Control Signals

3-9

3.11

GPIO Signals

3-10

3.12

ROM Flash and Memory Interface Signals

3-11

3.13

Test Interface Signals

3-12

3.14

Power and Ground Signals

3-13

3.15

Decode of MAD Pins

3-14

4.1

PCI Configuration Register Map

4-2

4.2

SCSI Register Address Map

4-19

4.3Examples of Synchronous Transfer Periods and Rates

for SCSI-1

4-32

4.4Example Transfer Periods and Rates for Fast SCSI-2

 

and Ultra SCSI

4-33

4.5

Maximum Synchronous Offset

4-34

4.6

SCSI Synchronous Data FIFO Word Count

4-44

5.1

SCRIPTS Instructions

5-3

xiiContents

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LSI 53C875A technical manual Tables