LSI 53C875A 6.4 PCI and External Memory Interface Timing Diagrams

PCI and External Memory InterfaceTiming Diagrams 6-11
Figure 6.8 Interrupt Output
6.4 PCI and External Memory Interface Timing Diagrams
Figure 6.9 through Figure 6.32 represent signal activity when the
LSI53C875A accesses the PCI bus. This section includes timing
diagrams for access to three groups of memory configurations. The first
group applies to Target Timing. The second group applies to Initiator
Timing. The third group applies to External Memory Timing.
Note: Multiple byte accesses to the external memory bus
increase the read or write cycle by 11 clocks for each
additional byte.
Timing diagrams included in this section are:
•Target Timing
– PCI Configuration Register Read
– PCI Configuration Register Write
– 32-B it Operating Register/SCRIPTS RAM Read
– 64-B it Address Operating Register/SCRIPTS RAM Read
– 32-B it Operating Register/SCRIPTS RAM Write
– 64-B it Address Operating Register/SCRIPTS RAM Write
•Initiator Timing
– Nonburst Opcode Fetch, 32-Bit Address and Data
– Burst O pcode Fetch, 32-Bit Address and Data
– Back-to-B ackRea d, 32-Bit Address and Data
– Back-to-B ackWr ite, 32-Bit Address and Data
CLK
IRQ/
t3t1
t2