Figure 6.27 Normal/Fast Memory (128 Kbytes) Multiple Byte Access Read Cycle

0

2

4

6

8

10

12

14

16

17

CLK (Driven by System)

FRAME/ (Driven by Master)

Addr In

AD

(Driven by LSI53C875A- Master-Addr; Data)

 

CMD

C_BE[3:0]/

 

 

Byte Enable

(Driven by Master)

 

 

 

 

 

PAR

In

(Driven by LSI53C875A-

Master-Addr; Data)

 

IRDY/ (Driven by Master)

TRDY/ (Driven by LSI53C875A)

STOP/ (Driven by LSI53C875A)

DEVSEL/ (Driven by LSI53C875A)

MAD

(Addr Driven by LSI53C875A;

Data driven by Memory)

MAS1/ (Driven by LSI53C875A)

MAS0/ (Driven by LSI53C875A)

MCE/ (Driven by LSI53C875A)

MOE/ (Driven by LSI53C875A)

MWE/ (Driven by LSI53C875A)

Upper

Middle

Lower

Address

Address

Address

6-44

Electrical Specifications

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Image 282
LSI 53C875A technical manual CBE30 Byte Enable