DWR

Data Write

3

 

This bit is used to define if a data write is considered to

 

be a local memory access.

 

DRD

Data Read

2

 

This bit is used to define if a data read is considered to

 

be a local memory access.

 

PSCPT

Pointer SCRIPTS

1

 

This bit is used to define if a pointer to a SCRIPTS

 

 

indirect or table indirect fetch is considered to be a local

 

memory access.

 

SCPTS

SCRIPTS

0

 

This bit is used to define if a SCRIPTS fetch is

 

 

considered to be a local memory access.

 

Register: 0x47

General Purpose Pin Control Zero (GPCNTL0)

Read/Write

7

6

5

4

 

2

1

0

ME

FE

LEDC

 

GPIO

 

 

GPIO

 

 

 

 

 

 

 

 

 

0

0

0

0

1

1

1

 

1

 

 

 

 

 

 

 

 

 

This register is used to determine if the pins controlled by the General Purpose (GPREG0) register are inputs or outputs. Bits [4:0] in GPCNTL0 correspond to bits [4:0] in the GPREG0 register. When the bits are enabled as inputs, internal pull-downs are enabled for GPIO[4:2] and internal pull-ups are enabled for GPIO[1:0].

The data written to each bit of the GPREG0 register is output to the appropriate GPIO pin if it is set to the output mode in the GPCNTL0 register.

ME

Master Enable

7

 

The internal bus master signal is presented on GPIO1 if

 

this bit is set, regardless of the state of bit 1 (GPIO1).

 

FE

Fetch Enable

6

 

The internal opcode fetch signal is presented on GPIO0

 

if this bit is set, regardless of the state of bit 0 (GPIO0).

4-82Registers

Page 174
Image 174
LSI 53C875A technical manual Dwr, Drd, Pscpt, Scpts Scripts, General Purpose Pin Control Zero GPCNTL0 Read/Write