LSI 53C875A Bits Used for Parity Control and Generation, Bit Name Location Description

Table 2.3	Bits Used for Parity Control and Generation
Bit Name		Location	Description
Assert SATN/ on		SCSI Control Zero	Causes the LSI53C875A to automatically assert SATN/
Parity Errors		(SCNTL0), Bit 1	when it detects a SCSI parity error while operating as an
			initiator.
Enable Parity		SCSI Control Zero	Enables the LSI53C875A to check for parity errors. The
Checking		(SCNTL0), Bit 3	LSI53C875A checks for odd parity.
Assert Even SCSI		SCSI Control One	Determines the SCSI parity sense generated by the
Parity		(SCNTL1), Bit 2	LSI53C875A to the SCSI bus.
Disable Halt on		SCSI Control One	Causes the LSI53C875A not to halt operations when a
SATN/ or a Parity		(SCNTL1), Bit 5	parity error is detected in target mode.
Error (Target Mode
Only)
Enable Parity Error		SCSI Interrupt	Determines whether the LSI53C875A generates an
Interrupt		Enable Zero	interrupt when it detects a SCSI parity error.
		(SIEN0), Bit 0
Parity Error		SCSI Interrupt	This status bit is set whenever the LSI53C875A detects a
		Status Zero	parity error on the SCSI bus.
		(SIST0), Bit 0
Status of SCSI		SCSI Status Zero	This status bit represents the active HIGH current state of
Parity Signal		(SSTAT0), Bit 0	the SCSI SDP0 parity signal.
SCSI SDP1 Signal		SCSI Status Two	This bit represents the active HIGH current state of the
		(SSTAT2), Bit 0	SCSI SDP1 parity signal.
Latched SCSI Parity		SSTAT 2, Bit 3 and	These bits reflect the SCSI odd parity signal
		SCSI Status One	corresponding to the data latched into the SCSI Input
		(SSTAT1), Bit 3	Data Latch (SIDL) register.
Master Parity Error		Chip Test Four	Enables parity checking during PCI master data phases.
Enable		(CTEST4), Bit 3
Master Data Parity		DMA Status	Set when the LSI53C875A, as a PCI master, detects a
Error		(DSTAT), Bit 6	target device signaling a parity error during a data phase.
Master Data Parity		DMA Interrupt	By clearing this bit, a Master Data Parity Error does not
Error Interrupt		Enable (DIEN),	cause assertion of INTA/ (or INTB/), but the status bit is
Enable		Bit 6	set in the DMA Status (DSTAT) register.

SCSI Functional Description 2-25