LSI 53C875A technical manual Memory Read Caching, Memory Write Caching

•To issue Memory Read Multiple commands, the Read Multiple enable bit in the DMA Mode (DMODE) register must be set.

•To issue Memory Write and Invalidate commands, both the Write and Invalidate enables in the Chip Test Three (CTEST3) register and the PCI configuration command register must be set.

If the corresponding cache command being issued is not enabled then the cache logic falls back to the next command enabled. Specifically, if Memory Read Multiple is not enabled and Memory Read Lines are, read lines are issued in place of read multiple. If no cache commands are enabled, cache write alignment still occurs but no cache commands are issued, only memory reads and memory writes.

2.1.3.3 Memory Read Caching

The type of Memory Read command issued depends on the starting location of the transfer and the number of bytes being transferred. During reads, no cache alignment is done (this is not required nor optimal per PCI 2.2 specification) and reads will always be either a programmed burst length in size, as set in the DMA Mode (DMODE) and Chip Test Three (CTEST3) registers. In the case of a transfer which is smaller than the burst length, all bytes for that transfer are read in one PCI burst transaction. If the transfer will cross a Dword boundary (A[1:0] = 0b00) a Memory Read Line command is issued. When the transfer will cross a cache boundary (depends on cache line size programmed into the PCI configuration register), a Memory Read Multiple command is issued. If a transfer will not cross a Dword or cache boundary or if cache mode is not enabled a Memory Read command is issued.

2.1.3.4 Memory Write Caching

Writes are aligned in a single burst transfer to get to a cache boundary. At that point, Memory Write and Invalidate commands are issued and continue at the burst length programmed into the DMA Mode (DMODE) register. Memory Write and Invalidate commands are issued as long as the remaining byte count is greater than the Memory Write and Invalidate threshold. When the byte count goes below this threshold, a single Memory Write burst is issued to complete the transfer. The general pattern for PCI writes is:

•A single Memory Write to align to a cache boundary.

PCI Functional Description 2-11