LSI 53C875A Disable Single Initiator Response, S16 Bit System, Ttm, Timer Test Mode

Models: 53C875A

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for test purposes or to lower IDD during a power-down mode.

DSI

Disable Single Initiator Response

4

 

If this bit is set, the LSI53C875A ignores all bus-initiated

 

selection attempts that employ the single initiator option

 

from SCSI-1. In order to select the LSI53C875A while this

 

bit is set, the LSI53C875A’s SCSI ID and the initiator’s

 

 

SCSI ID must both be asserted. Assert this bit in

 

 

SCSI-2 systems so that a single bit error on the SCSI bus

 

is not interpreted as a single initiator response.

 

S16

16-Bit System

3

 

If this bit is set, all devices in the SCSI system

 

 

implementation are assumed to be 16-bit. This causes

 

 

the LSI53C875A to always check the parity bit for SCSI

 

IDs [15:8] during bus-initiated selection or reselection,

 

 

assuming parity checking has been enabled. If an 8-bit

 

 

SCSI device attempts to select the LSI53C875A while

 

 

this bit is set, the LSI53C875A will ignore the selection

 

 

attempt. This is because the parity bit for IDs [15:8] will

 

not be driven. See the description of the Enable Parity

 

 

Checking bit in the SCSI Control Zero (SCNTL0) register

 

for more information.

 

TTM

Timer Test Mode

2

 

Asserting this bit facilitates testing of the selection

 

 

time-out, general purpose, and handshake-to-handshake

 

timers by greatly reducing all three time-out periods.

 

 

Setting this bit starts all three timers and if the respective

 

bits in the SCSI Interrupt Enable One (SIEN1) register

 

 

are asserted, the LSI53C875A generates interrupts at

 

 

time-out. This bit is intended for internal manufacturing

 

 

diagnosis and should not be used.

 

CSFClear SCSI FIFO1

Setting this bit causes the “full flags” for the SCSI FIFO to be cleared. This empties the FIFO. This bit is self-clearing. In addition to the SCSI FIFO pointers, the SCSI Input Data Latch (SIDL), SCSI Output Data Latch (SODL), and (SODR, a hidden buffer register which is not accessible) full bits in the SCSI Status Zero (SSTAT0) and SCSI Status Two (SSTAT2) are cleared.

4-92Registers

Page 184
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LSI 53C875A technical manual Disable Single Initiator Response, S16 Bit System, Ttm, Timer Test Mode, CSFClear Scsi FIFO1