PCI and External Memory InterfaceTiming Diagrams 6-49
Figure 6.30 Slow Memory (=128 Kbytes) Write CycleTable 6.34 Slow Memory (128 Kbytes) Write Cycle
Symbol Parameter Min Max Unit
t11 Address setup to MAS/ HIGH 25 ns
t12 Address hold from MAS/ HIGH 15 ns
t13 MAS/ pulse width 25 ns
t20 Data setup to MWE/ LOW 30 ns
t21 Data hold from MWE/ HIGH 20 ns
t22 MWE/ pulse width 100 ns
t23 Address setup to MWE/ LOW 60 ns
t24 MCE/ LOW to MWE/ HIGH 120 ns
t25 MCE/ LOW to MWE/ LOW 25 ns
t26 MWE/ HIGH to MCE/ HIGH 25 ns
CLK
MAD
(Drivenby LSI53C875A)
MAS1/
(Drivenby LSI53C875A)
MAS0/
(Drivenby LSI53C875A)
MCE/
(Drivenby LSI53C875A)
MOE/
(Drivenby LSI53C875A)
MWE/
(Drivenby LSI53C875A)
Higher
Address Lower
Address
t
12
Middle
Address ValidWrite Data
t
11
t
13
t
21
t
22
t
20
t
23
t
24
t
25
t
26