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LSI 53C875A technical manual Scsi Register Address Map

Models: 53C875A

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Table 4.2	SCSI Register Address Map
31		16 15					0
SCNTL3		SCNTL2		SCNTL1		SCNTL0		0x00
GPREG0		SDID		SXFER		SCID		0x04
SBCL		SSID		SOCL		SFBR		0x08
SSTAT2		SSTAT1		SSTAT0		DSTAT		0x0C
		DSA						0x10
MBOX1		MBOX0		ISTAT1		ISTAT0		0x14
CTEST3		CTEST2		CTEST1		CTEST0		0x18
		TEMP						0x1C
CTEST6		CTEST5		CTEST4		DFIFO		0x20
DCMD				DBC				0x24
		DNAD						0x28
		DSP						0x2C
		DSPS						0x30
		SCRATCH A						0x34
DCNTL		SBR		DIEN		DMODE		0x38
		ADDER						0x3C
SIST1		SIST0		SIEN1		SIEN0		0x40
GPCNTL0		MACNTL		SWIDE		SLPAR		0x44
RESPID1		RESPID0		STIME1		STIME0		0x48
STEST3		STEST2		STEST1		STEST0		0x4C
Reserved		STEST4			SIDL			0x50
CCNTL1		CCNTL0			SODL			0x54
Reserved		Reserved			SBDL			0x58
		SCRATCH B						0x5C
		SCRATCH C–SCRATCH R						0x60–0x9F
		MMRS						0xA0
		MMWS						0xA4
		SFS						0xA8
		DRS						0xAC
		SBMS						0xB0
		DBMS						0xB4
		DNAD64						0xB8
		Reserved						0xBC
		PMJAD1						0xC0
		PMJAD2						0xC4
		RBC						0xC8
		UA						0xCC
		ESA						0xD0
		IA						0xD4
Reserved				SBC				0xD8
		CSBC						0xDC
		Reserved						0xE0–0xFF

SCSI Registers

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Image 111

LSI 53C875A technical manual Scsi Register Address Map

Contents

C e m b e r 2 0 0 Technical ManualTrademark Acknowledgment Organization AudienceAnsi Revision Date Remarks PCI Special Interest GroupConventions Used in This Manual Revision RecordViPreface Contents Chapter Signal Descriptions Chapter Registers Figures Contents Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR XivContents Chapter General Description Typical LSI53C875A System Application Benefits of Ultra Scsi New Features in the LSI53C875ALSI53C875A Benefits Summary TolerANT TechnologyScsi Performance PCI Performance IntegrationEase of Use Scripts RAM FlexibilityTestability ReliabilityChapter Functional Description PCI Addressing PCI Functional DescriptionConfiguration Space PCI Bus Commands and Functions SupportedCBE30 Command Type Supported as Master Supported as Slave PCI Bus Commands and Encoding Types for the LSI53C875AInterrupt Acknowledge Command Special Cycle CommandMemory Read Command 2.3 I/O Read Command2.4 I/O Write Command Reserved CommandMemory Read Multiple Command Dual Address Cycle DAC CommandMemory Read Line Command PCI Functional Description Memory Write and Invalidate Command PCI Cache Mode Issuing Cache Commands Enabling Cache ModeMemory Write Caching Memory Read CachingHost Memory PCI Cache Mode AlignmentRead Example ExamplesWrite Example Write Example Memory-to-Memory Moves Scsi Functional DescriptionScripts Processor Phase Mismatch Handling in ScriptsInternal Scripts RAM Hardware Control of Scsi Activity LED 3 64-Bit Addressing in ScriptsDesigning an Ultra Scsi System Using the Scsi Clock QuadruplerPrefetching Scripts Instructions Load and Store Instructions Opcode Fetch Burst CapabilityScsi Loopback Mode Jtag Boundary Scan TestingParity Options Bit Name Location Description Bits Used for Parity Control and GenerationScsi Parity Control Scsi Parity Errors and InterruptsParity Checking/Generation DMA FifoData Paths DMA Fifo SectionsAsynchronous Scsi Send LSI53C875A Host Interface Scsi Data PathsSynchronous Scsi Send Synchronous Scsi Receive Asynchronous Scsi ReceiveScsi Termination Scsi Bus InterfaceRegulated Termination for Ultra Scsi Select/Reselect During Selection/ReselectionDetermining the Data Transfer Rate Synchronous OperationDetermining the Synchronous Transfer Rate Ultra Scsi Synchronous Data Transfers Scsi Control Three SCNTL3 Register, Bits 64 SCF20Scsi Control Three SCNTL3 Register, Bits 20 CCF20 Scsi Transfer Sxfer Register, Bits 75 TP20Interrupt Handling Polling and Hardware InterruptsRegisters Functional Description Fatal vs. Nonfatal Interrupts Masking Stacked Interrupts Halting in an Orderly Fashion Read Interrupt Status Zero ISTAT0 Sample Interrupt Service RoutineChained Block Moves Wide Scsi Send Bit Block Move and Chained Block Move InstructionsWide Scsi Receive Bit Swide RegisterSodl Register Chained Block Move Scripts Instruction Parallel ROM Interface MAD31 Available Memory Space Parallel ROM SupportSerial Eeprom Interface Default Download ModeByte Name Description Power ManagementNo Download Mode Mode a Serial Eeprom Data FormatConfiguration Register Bits Power State D0Power State D1 Power StatesPower State D3 Power State D2Functional Description Chapter Signal Descriptions LSI53C875A Functional Signal Grouping LSI53C875A Functional Signal GroupingLSI53C875A Internal Pull-ups Signal DescriptionsInternal Pull-ups on LSI53C875A Signals Signal Name Pull-up Current Conditions for Pull-upType Strength Description PCI Bus Interface SignalsSystem Signals System SignalsAddress and Data Signals Address and Data SignalsBus Command and Byte Enables are Interface Control Signals Interface Control SignalsInitialization Device Select is used as a chip select Error Reporting Signals Arbitration SignalsError Reporting Signals Arbitration SignalsInterrupt Signal Scsi Bus Interface SignalsInterrupt Signal Scsi Bus Interface Signal10 Scsi Control Signals Scsi SignalsScsi Control Signals Scsi SignalsScsi General Purpose I/O pin. This pin Gpio Signals11 Gpio Signals Scsi General Purpose I/O pin. Optionally12 ROM Flash and Memory Interface Signals ROM Flash and Memory Interface SignalsTest Interface Signals 13 Test Interface SignalsMemory Address/Data Bus. This bus is used 14 Power and Ground Signals Power and Ground SignalsMAD Bus Programming 15 Decode of MAD PinsMAD Bus Programming Signal Descriptions Chapter Registers PCI Configuration RegistersRegisters Vendor ID Read OnlyVIDVendor ID150 DIDDevice ID150 Command Read/WriteEnable Parity Error Response Device ID Read OnlyEIS WIEEBM EMSRTA DPESSE RMARIDRevision ID70 RegisterDPR Revision ID Rev ID Read OnlyRegister 0x0C Registers 0x09-0x0BRegister 0x0D Register 0x0ERegister 0x0F BAR1 BAR0Registers 0x2C-0x2D Registers 0x18-0x1BRegisters 0x1C-0x27 Registers 0x28-0x2BSubsystem ID 150 Registers 0x2E-0x2FSubsystem ID Read Only SIDExpansion ROM Base Address Read/Write ErbaExpansion ROM Base Address 310 Interrupt Line Read/Write ILInterrupt Line70 Registers 0x35-0x3BRegister 0x3C Capabilities Pointer Read Only CPCapabilities Pointer70MGMINGNT70 Register 0x3DRegister 0x3E Register 0x3FPmes APS D2SD1S DSIBridge Support Extensions Pmcsrbse Read Only DsclDslt PENScsi Registers Data Read OnlyDATAData70 Scsi Register Address Map Simple Arbitration ARB10 Arbitration Mode Bits 1Arbitration Mode Scsi Control Zero SCNTL0 Read/WriteStart Start Sequence5 Full Arbitration, Selection/ReselectionWatn EPCAAP EXC ADBDHP Iarb CONRST AespSSTStart Scsi Transfer0 Scsi Disconnect Unexpected Chained ModeScsi Control Two SCNTL2 Read/Write SDUVUE0 SlpmdSlphben WSSUSE Ultra Scsi EnableWSRWide Scsi Receive0 Scsi Control Three SCNTL3 Read/WriteCCF20 Clock Conversion Factor Enable Wide ScsiSCF20 Synchronous Clock Conversion Factor EWSRRE SREENC TP20 Scsi Synchronous Transfer Period Scsi Transfer Sxfer Read/WriteSynch CLK MHz Transfer RateBits Period ns Mbytes/s MO40 Max Scsi Synchronous Offset Synchronous Offset Maximum Synchronous OffsetGpio Scsi Destination ID Sdid Read/WriteEncoded Destination Scsi ID General Purpose GPREG0 Read/WriteSfbr Scsi First Byte Received70 Scsi First Byte Received Sfbr Read/WriteSEL REQACK BSYEnid Register 0x0ARegister 0x0B VALSSEL/ Status SREQ/ StatusSACK/ Status SBSY/ StatusSIR MdpeAbrt SSIScsi Registers ILF ORFOLF AIP LOAWOA Scsi Synchronous Data Fifo Word Count Bytes or WordsSSTAT2 bit SDP0L ILF1 ORF1OLF1 DSA SPL1Ldsc SDP1Srst Software Reset6 Interrupt Status Zero ISTAT0 Read/WriteAbort Operation Semaphore Signal ProcessSigp SEMDipdma Interrupt Pending0 Sipscsi Interrupt Pending1Flsh SrunSyncirqd MBOX1 Mailbox One70 Mailbox Zero MBOX0 Read/WriteMBOX0 Mailbox Zero70 Mailbox One MBOX1 Read/WriteFFLByte Full in DMA FIFO70 Chip Test Zero CTEST0 Read/WriteFMTByte Empty in DMA FIFO70 Chip Test One CTEST1 Read OnlyRegister 0x1A DdirCIO Teop DreqDack Register 0x1B FLFCLF Registers 0x1C-0x1F TempDMA Fifo Dfifo 58Registers Srtm BdisFBL3 ZSDClock Address Incrementor FBL20 Fifo Byte ControlChip Test Five CTEST5 Read/Write AdckBL2 BbckDFS MasrDBC Dfdma FIFO70Dcmd DMA Command70 DMA Command Dcmd Read/WriteRegisters 0x2C-0x2F DnadDSP Scratcha Scratch Register a 310 DMA Scripts Pointer Save Dsps Read/WriteDsps DMA Scripts Pointer Save310 Scratch Register a Scratcha Read/WriteBL10 Burst Length DMA Mode Dmode Read/WriteSiom Source I/O Memory EnableDestination I/O Memory Enable ERLEnable Read Line3BOF Enable Read MultipleBurst Opcode Fetch Enable ErmpIllegal Instruction Detected DMA Interrupt Enable Dien Read/WriteMaster Data Parity Error Bus Fault Scripts Interrupt Instruction Received ReservedPFF Register 0x3ARegister 0x3B ClseSingle Step Mode SSMIrqmirq Mode3 COMLSI53C700 Compatibility0 IRQ DisableSTDStart DMA Operation2 IrqdRegisters 0x3C-0x3F 0x40Adder UDC CMPRSL SGEGEN STOHTHHandshake-to-Handshake Timer Expired0 Initiator Mode Phase Mismatch Target Mode SATN/ ActiveScsi Interrupt Status Zero SIST0 Read Only This bit is set when an arbitration only or full arbitration Scsi Interrupt Status One SIST1 Read Only Parity ErrorScsi RST/ Received PARSlpar Scsi Longitudinal Parity70 Handshake-to-Handshake Timer ExpiredHTH Scsi Longitudinal Parity Slpar Read/WriteData Bytes Running Slpar TYP Memory Access Control Macntl Read/WriteScsi Wide Residue Swide Read/Write Swide Scsi Wide Residue70Scpts Scripts DWRDRD PscptHTH30 Handshake-to-HandshakeTimer Period Gpio EnableGpiogpio Enable10 Scsi Timer Zero STIME0 Read/WriteSEL30 Selection Time-Out30 Hthba GensfHthsf Register 0x4B Register 0x4AART Register 0x4CSsaid SLTQEN Register 0x4DSclk ISOROF Register 0x4EQsel SCELOW SZMAWS EXTSTR Register 0x4FTTM Disable Single Initiator ResponseTimer Test Mode S16 Bit SystemSTW Scsi Input Data Latch Sidl Read OnlySidlscsi Input Data Latch150 Lock Register 0x53Pmjctl Jump Control6 Enable Phase Mismatch JumpChip Control 0 CCNTL0 Read/Write EnpmjEnndj DisfcDils Zmode Ddac64TIMOD Scsi Bus Data Lines Sbdl Read Only Enable 64-Bit Direct BmovEN64TIBMV EN64DBMVRegisters 0x60-0x9F 64-Bit Scripts SelectorsRegister 0x5A-0x5B Registers 0x5C-0x5FMemory Move Read Selector Mmrs Registers 0xA0-0xA3Memory Move Read Selector Mmrs Read/Write MmrsSFS Registers 0xA4-0xA7Registers 0xA8-0xAB MmwsSbms Registers 0xAC-0xAFRegisters 0xB0-0xB3 DRSRegisters 0xBC-0xBF Phase Mismatch Jump RegistersRegisters 0xB4-0xB7 Registers 0xB8-0xBBPMJAD2 Registers 0xC0-0xC3Registers 0xC4-0xC7 PMJAD1Registers 0xC8-0xCB Registers 0xCC-0xCFRBC Entry Storage Address 310 Registers 0xD0-0xD3Entry Storage Address ESA Read/Write ESARegisters 0xD4-0xD7 Registers 0xD8-0xDASBC Csbc Register 0xDBRegisters 0xDC-0xDF Registers 0xE0-0xFFScsi Scripts Low Level Register Interface ModeHigh Level Scsi Scripts Mode Sample Operation Scripts InstructionsInstruction Description Scsi Scripts Instruction Set Scripts Overview First Dword Block Move InstructionDirect Addressing TIATable Indirect Bit Addressing Command Not Used Don’t Care Target Mode OPCOpCode27OPC Instruction Defined Initiator Mode SCSIP20 Scsi Phase2624 Scsi Information Transfer Phase Scsi PhaseTC230 Transfer Counter230 Start Address 310 Target Mode Initiator ModeI/O Instruction Second DwordInstruction Defined IT10 Instruction Type I/O Instruction 3130OPC20 OpCode 2927 Reselect InstructionClear Instruction Disconnect InstructionWait Select Instruction Set InstructionSelect Instruction Wait Reselect Instruction Wait Disconnect InstructionTITable Indirect Mode25 Relative Addressing ModeBit DirectTable Indirect RelativeTable Relative Command Table Offset Absolute Jump OffsetSet/Clear Satn Set/Clear Sack ReservedUse data8/SFBR Read/Write InstructionsIT10 Instruction Type Read/Write Instruction 3130 O20 Operator 2624A60 Register Address A60 2216 Read-Modify-Write CyclesRead/Write Instructions Move To/From Sfbr CyclesTransfer Control Instructions IT10 Instruction Type Transfer Control 3130 Transfer Control InstructionsJump Instruction Return Instruction Call InstructionInterrupt-on-the-Fly Instruction Interrupt InstructionJump/Call a Relative Address Scsi Phase ComparisonsRARelative Addressing Mode23 Jump/Call an Absolute AddressBit 2 is asserted JMPJump If True/False WVP Compare PhaseWait for Valid Phase Compare DataJump Address 310 Memory Move InstructionsDCV Data Compare ValueIT20 Instruction Type Memory Move 3129 Reserved 2825No Flush Dsps Register 310 Read/Write System Memory from ScriptsBit A1 Bit A0 Number of Bytes Allowed to Load and Store Load and Store InstructionsThird Dword Temp Register 310Bit Source Destination IT20 Instruction Type 3129DSA Relative Reserved 2726 No Flush Store instruction onlyDMA Control Dcntl register is set This bit has no effect unless the Prefetch Enable bitScsi Scripts Instruction Set DC Characteristics Chapter Electrical SpecificationsInput Capacitance Symbol Parameter Min Max Unit Test ConditionsAbsolute Maximum Stress Ratings1 Operating Conditions1Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER/, GPIO24 Bidirectional Signals-MAD70, MAS/10, MCE/, MOE/, MWEOutput Signal-TDO TolerANT Technology Electrical Characteristics Output Signals-IRQ/, MAC/TESTOUT, REQOutput Signal-SERR Pqfp Symbol Parameter Min1 Max Unit Test ConditionsRise and Fall Time Test Condition Input Current as a Function of Input Voltage AC Characteristics Symbol Parameter Min Max Unit12 External Clock1 Interrupt Output Reset InputPCI and External Memory Interface Timing Diagrams Electrical Specifications 15 PCI Configuration Register Read PCI Configuration Register ReadTarget Timing 10 PCI Configuration Register Write 16 PCI Configuration Register Write11 32-Bit Operating Register/SCRIPTS RAM Read 17 32-Bit Operating Register/SCRIPTS RAM Read12 64-Bit Address Operating Register/SCRIPTS RAM Read 18 64-Bit Address Operating Register/SCRIPTS RAM Read13 32-Bit Operating Register/SCRIPTS RAM Write 19 32-Bit Operating Register/SCRIPTS RAM Write14 64-Bit Address Operating Register/SCRIPTS RAM Write 20 64-Bit Address Operating Register/SCRIPTS RAM Write21 Nonburst Opcode Fetch, 32-Bit Address and Data Initiator Timing15 Nonburst Opcode Fetch, 32-Bit Address and Data 22 Burst Opcode Fetch, 32-Bit Address and Data 16 Burst Opcode Fetch, 32-Bit Address and Data 23 Back-to-Back Read, 32-Bit Address and Data 17 Back-to-Back Read, 32-Bit Address and Data 24 Back-to-Back Write, 32-Bit Address and Data 18 Back-to-Back Write, 32-Bit Address and Data 25 Burst Read, 32-Bit Address and Data 19 Burst Read, 32-Bit Address and Data 26 Burst Read, 64-Bit Address and Data 20 Burst Read, 64-Bit Address and Data 27 Burst Write, 32-Bit Address and Data 21 Burst Write, 32-Bit Address and Data 28 Burst Write, 64-Bit Address and 32-Bit Data 22 Burst Write, 64-Bit Address and 32-Bit Data 29 External Memory Read External Memory Timing23 External Memory Read STOP/ Driven by LSI53C875A 30 External Memory Write External Memory Write timings start on 24 External Memory Write Data Byte Enable Address out from MOE/, MCE/ High Driven by LSI53C875A Higher Valid Write Data CBE30 Byte Enable Data Byte Enable Out Lower Address Data LSI53C875A-Data Data Byte Enable Data Out Slow Memory ≤ 128 Kbytes Read Cycle Symbol Parameter Min30 Slow Memory ≤ 128 Kbytes Write Cycle Slow Memory ≤ 128 Kbytes Write Cycle≤ 64 Kbytes ROM Read Cycle 32 ≤ 64 Kbyte ROM Write Cycle ≤ 64 Kbyte ROM Write Cycle37 Initiator Asynchronous Send Scsi Timing Diagrams34 Initiator Asynchronous Receive 38 Initiator Asynchronous Receive35 Target Asynchronous Send 39 Target Asynchronous Send41 SCSI-1 Transfers 5.0 Mbytes 40 Target Asynchronous ReceiveSymbol Parameter Min Max Unit 37 Initiator and Target Synchronous Transfer 38 LSI53C875A 160-Pin Pqfp Mechanical Drawing Package DiagramsPin Pqfp P3 Mechanical Drawing Sheet 2 44 160 Pqfp Pin List by Location Signal PinPin BGA Mechanical Drawing NC1 45 169 BGA Pin List by LocationAppendix a Register Summary Table A.2 LSI53C875A Scsi Register Map Register Summary Scratch Registers C-RSCRATCHC-SCRATCHR Table A.2 LSI53C875A Scsi Register Map Register Summary Appendix B External Memory Interface Diagram Examples Figure B.2 64 Kbyte Interface with 150 ns Memory External Memory Interface Diagram Examples Figure B.4 512 Kbyte Interface with 150 ns Memory Index SymbolsIX-2Index SGE 4-74,4-77 SI NumericsIX-4Index IX-5 IX-6Index IX-7 IX-8Index IX-9 IX-10Index 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