LSI 53C875A technical manual Address and Data Signals, Bus Command and Byte Enables are

3.3.2 Address and Data Signals

	Table 3.3 describes Address and Data signals.
Table 3.3	Address and Data Signals
Name	PQFP	BGA	Type	Strength	Description
AD[31:0]	150, 151,	B5, C5, A4,	T/S	8 mA	Physical Dword Address and Data are
	153, 154,	B4, A3, C4,		PCI	multiplexed on the same PCI pins. A bus
	156, 157,	D4, A2, C2,			transaction consists of an address phase
	159, 160, 3,	E5, C1, D3,			followed by one or more data phases.
	5, 6, 7, 9,	E4-E1, H5,			During the first clock of a transaction,
	11–13, 28–	J1, J2, H6,			AD[31:0] contain a 32-bit physical byte
	30, 32, 34–	K2, J4, L1,			address. If the command is a DAC,
	36, 38, 40,	L2, M1, N1,			implying a 64-bit address, a second
	41, 43, 44,	M3, L3, N3,			address phase is required. During the
	46, 47, 49,	L4, K5, N4			first phase, AD[31:0] will contain the
	50				lower 32 bits of the address followed by
					a second phase with AD[31:0] containing
					the upper 32 bits of the address. During
					subsequent clocks, AD[31:0] contain
					data. PCI supports both read and write
					bursts. AD[7:0] define the least
					significant byte, and AD[31:24] define the
					most significant byte.
C_BE[3:0]	1, 15, 26,	A1, F3, H3,	T/S	8 mA	Bus Command and Byte Enables are
	39	K4		PCI	multiplexed on the same PCI pins.
					During the address phase of a
					transaction, C_BE[3:0]/ define the bus
					command. During the data phase,
					C_BE[3:0]/ are used as byte enables.
					The byte enables determine which byte
					lanes carry meaningful data. C_BE[0]/
					applies to byte 0, and C_BE[3]/ to byte 3.
PAR	25	H1	T/S	8 mA	Parity is the even parity bit that protects
				PCI	the AD[31:0] and C_BE[3:0]/ lines.
					During the address phase, both the
					address and command bits are covered.
					During data phase, both data and byte
					enables are covered.

PCI Bus Interface Signals 3-5