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LSI 53C875A technical manual Input Current as a Function of Input Voltage

Models: 53C875A

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Figure 6.4 Input Current as a Function of Input Voltage

Input Current (milliAmperes)

+40

+20

14.4 V

8.2 V

0

−0.7 V

HIGH-Z

− 20OUTPUT ACTIVE

−40

− 4

0

4

8

12

16

Input Voltage (Volts)

Figure 6.5 Output Current as a Function of Output Voltage
(milliAmperes)	0						(milliAmperes)	100
(milliAmperes)							(milliAmperes)	60
	− 200							80
	− 200
Current	− 400						Current	40
OutputSink	− 600						SourceOutput	20
	− 600

	− 800							0
	0	1	2	3	4	5		0	1	2	3	4	5
		Output Voltage (Volts)								Output Voltage (Volts)

6-8	Electrical Specifications

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LSI 53C875A technical manual Input Current as a Function of Input Voltage

Contents

Technical Manual C e m b e r 2 0 0Trademark Acknowledgment Audience OrganizationAnsi Revision Record PCI Special Interest GroupConventions Used in This Manual Revision Date RemarksViPreface Contents Chapter Signal Descriptions Chapter Registers Figures Contents Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR XivContents Chapter General Description Typical LSI53C875A System Application New Features in the LSI53C875A Benefits of Ultra ScsiTolerANT Technology LSI53C875A Benefits SummaryScsi Performance PCI Performance IntegrationEase of Use Flexibility Scripts RAMReliability TestabilityChapter Functional Description PCI Functional Description PCI AddressingPCI Bus Commands and Functions Supported Configuration SpaceSpecial Cycle Command PCI Bus Commands and Encoding Types for the LSI53C875AInterrupt Acknowledge Command CBE30 Command Type Supported as Master Supported as SlaveReserved Command 2.3 I/O Read Command2.4 I/O Write Command Memory Read CommandMemory Read Multiple Command Dual Address Cycle DAC CommandMemory Read Line Command PCI Functional Description Memory Write and Invalidate Command PCI Cache Mode Enabling Cache Mode Issuing Cache CommandsMemory Read Caching Memory Write CachingPCI Cache Mode Alignment Host MemoryExamples Read ExampleWrite Example Write Example Scsi Functional Description Memory-to-Memory MovesPhase Mismatch Handling in Scripts Scripts ProcessorInternal Scripts RAM 3 64-Bit Addressing in Scripts Hardware Control of Scsi Activity LEDUsing the Scsi Clock Quadrupler Designing an Ultra Scsi SystemPrefetching Scripts Instructions Opcode Fetch Burst Capability Load and Store InstructionsJtag Boundary Scan Testing Scsi Loopback ModeParity Options Bits Used for Parity Control and Generation Bit Name Location DescriptionScsi Parity Errors and Interrupts Scsi Parity ControlDMA Fifo Parity Checking/GenerationDMA Fifo Sections Data PathsLSI53C875A Host Interface Scsi Data Paths Asynchronous Scsi SendSynchronous Scsi Send Asynchronous Scsi Receive Synchronous Scsi ReceiveScsi Bus Interface Scsi TerminationSelect/Reselect During Selection/Reselection Regulated Termination for Ultra ScsiSynchronous Operation Determining the Data Transfer RateDetermining the Synchronous Transfer Rate Scsi Transfer Sxfer Register, Bits 75 TP20 Scsi Control Three SCNTL3 Register, Bits 64 SCF20Scsi Control Three SCNTL3 Register, Bits 20 CCF20 Ultra Scsi Synchronous Data TransfersInterrupt Handling Polling and Hardware InterruptsRegisters Functional Description Fatal vs. Nonfatal Interrupts Masking Stacked Interrupts Halting in an Orderly Fashion Sample Interrupt Service Routine Read Interrupt Status Zero ISTAT0Chained Block Moves Block Move and Chained Block Move Instructions Wide Scsi Send BitWide Scsi Receive Bit Swide RegisterSodl Register Chained Block Move Scripts Instruction Parallel ROM Interface Parallel ROM Support MAD31 Available Memory SpaceDefault Download Mode Serial Eeprom InterfaceMode a Serial Eeprom Data Format Power ManagementNo Download Mode Byte Name DescriptionPower States Power State D0Power State D1 Configuration Register BitsPower State D2 Power State D3Functional Description Chapter Signal Descriptions LSI53C875A Functional Signal Grouping LSI53C875A Functional Signal GroupingSignal Name Pull-up Current Conditions for Pull-up Signal DescriptionsInternal Pull-ups on LSI53C875A Signals LSI53C875A Internal Pull-upsSystem Signals PCI Bus Interface SignalsSystem Signals Type Strength DescriptionAddress and Data Signals Address and Data SignalsBus Command and Byte Enables are Interface Control Signals Interface Control SignalsInitialization Device Select is used as a chip select Arbitration Signals Arbitration SignalsError Reporting Signals Error Reporting SignalsScsi Bus Interface Signal Scsi Bus Interface SignalsInterrupt Signal Interrupt SignalScsi Signals Scsi SignalsScsi Control Signals 10 Scsi Control SignalsScsi General Purpose I/O pin. Optionally Gpio Signals11 Gpio Signals Scsi General Purpose I/O pin. This pinROM Flash and Memory Interface Signals 12 ROM Flash and Memory Interface SignalsTest Interface Signals 13 Test Interface SignalsMemory Address/Data Bus. This bus is used Power and Ground Signals 14 Power and Ground Signals15 Decode of MAD Pins MAD Bus ProgrammingMAD Bus Programming Signal Descriptions PCI Configuration Registers Chapter RegistersRegisters Vendor ID Read OnlyVIDVendor ID150 Device ID Read Only Command Read/WriteEnable Parity Error Response DIDDevice ID150EMS WIEEBM EISRMA DPESSE RTARevision ID Rev ID Read Only RegisterDPR RIDRevision ID70Registers 0x09-0x0B Register 0x0CRegister 0x0D Register 0x0ERegister 0x0F BAR0 BAR1Registers 0x28-0x2B Registers 0x18-0x1BRegisters 0x1C-0x27 Registers 0x2C-0x2DSID Registers 0x2E-0x2FSubsystem ID Read Only Subsystem ID 150Expansion ROM Base Address Read/Write ErbaExpansion ROM Base Address 310 Capabilities Pointer Read Only CPCapabilities Pointer70 Registers 0x35-0x3BRegister 0x3C Interrupt Line Read/Write ILInterrupt Line70Register 0x3F Register 0x3DRegister 0x3E MGMINGNT70Pmes DSI D2SD1S APSPEN DsclDslt Bridge Support Extensions Pmcsrbse Read OnlyScsi Registers Data Read OnlyDATAData70 Scsi Register Address Map Scsi Control Zero SCNTL0 Read/Write ARB10 Arbitration Mode Bits 1Arbitration Mode Simple ArbitrationFull Arbitration, Selection/Reselection Start Start Sequence5Watn EPCAAP EXC ADBDHP Aesp CONRST IarbSSTStart Scsi Transfer0 SDU Chained ModeScsi Control Two SCNTL2 Read/Write Scsi Disconnect UnexpectedWSS SlpmdSlphben VUE0Scsi Control Three SCNTL3 Read/Write Ultra Scsi EnableWSRWide Scsi Receive0 USEEWS Enable Wide ScsiSCF20 Synchronous Clock Conversion Factor CCF20 Clock Conversion FactorRRE SREENC Scsi Transfer Sxfer Read/Write TP20 Scsi Synchronous Transfer PeriodSynch CLK MHz Transfer RateBits Period ns Mbytes/s MO40 Max Scsi Synchronous Offset Maximum Synchronous Offset Synchronous OffsetGeneral Purpose GPREG0 Read/Write Scsi Destination ID Sdid Read/WriteEncoded Destination Scsi ID GpioScsi First Byte Received Sfbr Read/Write Sfbr Scsi First Byte Received70BSY REQACK SELVAL Register 0x0ARegister 0x0B EnidSBSY/ Status SREQ/ StatusSACK/ Status SSEL/ StatusSSI MdpeAbrt SIRScsi Registers ILF ORFOLF AIP LOAWOA Scsi Synchronous Data Fifo Word Count Bytes or WordsSSTAT2 bit SDP0L ILF1 ORF1OLF1 SDP1 SPL1Ldsc DSASrst Software Reset6 Interrupt Status Zero ISTAT0 Read/WriteAbort Operation SEM Signal ProcessSigp SemaphoreSipscsi Interrupt Pending1 Dipdma Interrupt Pending0Flsh SrunSyncirqd Mailbox One MBOX1 Read/Write Mailbox Zero MBOX0 Read/WriteMBOX0 Mailbox Zero70 MBOX1 Mailbox One70Chip Test One CTEST1 Read Only Chip Test Zero CTEST0 Read/WriteFMTByte Empty in DMA FIFO70 FFLByte Full in DMA FIFO70Register 0x1A DdirCIO Teop DreqDack Register 0x1B FLFCLF Registers 0x1C-0x1F TempDMA Fifo Dfifo 58Registers ZSD BdisFBL3 SrtmAdck FBL20 Fifo Byte ControlChip Test Five CTEST5 Read/Write Clock Address IncrementorMasr BbckDFS BL2Dfdma FIFO70 DBCDMA Command Dcmd Read/Write Dcmd DMA Command70Registers 0x2C-0x2F DnadDSP Scratch Register a Scratcha Read/Write DMA Scripts Pointer Save Dsps Read/WriteDsps DMA Scripts Pointer Save310 Scratcha Scratch Register a 310DMA Mode Dmode Read/Write BL10 Burst LengthERLEnable Read Line3 Source I/O Memory EnableDestination I/O Memory Enable SiomErmp Enable Read MultipleBurst Opcode Fetch Enable BOFScripts Interrupt Instruction Received Reserved DMA Interrupt Enable Dien Read/WriteMaster Data Parity Error Bus Fault Illegal Instruction DetectedClse Register 0x3ARegister 0x3B PFFSingle Step Mode SSMIrqmirq Mode3 Irqd IRQ DisableSTDStart DMA Operation2 COMLSI53C700 Compatibility0Registers 0x3C-0x3F 0x40Adder SGE CMPRSL UDCSTO GENHTHHandshake-to-Handshake Timer Expired0 Initiator Mode Phase Mismatch Target Mode SATN/ ActiveScsi Interrupt Status Zero SIST0 Read Only This bit is set when an arbitration only or full arbitration PAR Parity ErrorScsi RST/ Received Scsi Interrupt Status One SIST1 Read OnlyScsi Longitudinal Parity Slpar Read/Write Handshake-to-Handshake Timer ExpiredHTH Slpar Scsi Longitudinal Parity70Data Bytes Running Slpar Swide Scsi Wide Residue70 Memory Access Control Macntl Read/WriteScsi Wide Residue Swide Read/Write TYPPscpt DWRDRD Scpts ScriptsScsi Timer Zero STIME0 Read/Write Gpio EnableGpiogpio Enable10 HTH30 Handshake-to-HandshakeTimer PeriodSEL30 Selection Time-Out30 Hthba GensfHthsf Register 0x4A Register 0x4BSLT Register 0x4CSsaid ARTISO Register 0x4DSclk QENSCE Register 0x4EQsel ROFEXT SZMAWS LOWRegister 0x4F STRS16 Bit System Disable Single Initiator ResponseTimer Test Mode TTMSTW Scsi Input Data Latch Sidl Read OnlySidlscsi Input Data Latch150 Register 0x53 LockEnpmj Enable Phase Mismatch JumpChip Control 0 CCNTL0 Read/Write Pmjctl Jump Control6Enndj DisfcDils Zmode Ddac64TIMOD EN64DBMV Enable 64-Bit Direct BmovEN64TIBMV Scsi Bus Data Lines Sbdl Read OnlyRegisters 0x5C-0x5F 64-Bit Scripts SelectorsRegister 0x5A-0x5B Registers 0x60-0x9FMmrs Registers 0xA0-0xA3Memory Move Read Selector Mmrs Read/Write Memory Move Read Selector MmrsMmws Registers 0xA4-0xA7Registers 0xA8-0xAB SFSDRS Registers 0xAC-0xAFRegisters 0xB0-0xB3 SbmsRegisters 0xB8-0xBB Phase Mismatch Jump RegistersRegisters 0xB4-0xB7 Registers 0xBC-0xBFPMJAD1 Registers 0xC0-0xC3Registers 0xC4-0xC7 PMJAD2Registers 0xC8-0xCB Registers 0xCC-0xCFRBC ESA Registers 0xD0-0xD3Entry Storage Address ESA Read/Write Entry Storage Address 310Registers 0xD4-0xD7 Registers 0xD8-0xDASBC Registers 0xE0-0xFF Register 0xDBRegisters 0xDC-0xDF CsbcLow Level Register Interface Mode Scsi ScriptsHigh Level Scsi Scripts Mode Sample Operation Scripts InstructionsInstruction Description Scsi Scripts Instruction Set Scripts Overview Block Move Instruction First DwordDirect Addressing TIATable Indirect Bit Addressing Command Not Used Don’t Care Target Mode OPCOpCode27OPC Instruction Defined Initiator Mode SCSIP20 Scsi Phase2624 Scsi Information Transfer Phase Scsi PhaseTC230 Transfer Counter230 Second Dword Target Mode Initiator ModeI/O Instruction Start Address 310Reselect Instruction IT10 Instruction Type I/O Instruction 3130OPC20 OpCode 2927 Instruction DefinedSet Instruction Disconnect InstructionWait Select Instruction Clear InstructionSelect Instruction Wait Disconnect Instruction Wait Reselect InstructionRelative Addressing Mode TITable Indirect Mode25Relative DirectTable Indirect BitCommand Table Offset Absolute Jump Offset Table RelativeSet/Clear Sack Reserved Set/Clear SatnO20 Operator 2624 Read/Write InstructionsIT10 Instruction Type Read/Write Instruction 3130 Use data8/SFBRRead-Modify-Write Cycles A60 Register Address A60 2216Move To/From Sfbr Cycles Read/Write InstructionsTransfer Control Instructions IT10 Instruction Type Transfer Control 3130 Transfer Control InstructionsJump Instruction Call Instruction Return InstructionInterrupt Instruction Interrupt-on-the-Fly InstructionJump/Call an Absolute Address Scsi Phase ComparisonsRARelative Addressing Mode23 Jump/Call a Relative AddressBit 2 is asserted JMPJump If True/False Compare Data Compare PhaseWait for Valid Phase WVPData Compare Value Memory Move InstructionsDCV Jump Address 310IT20 Instruction Type Memory Move 3129 Reserved 2825No Flush Read/Write System Memory from Scripts Dsps Register 310Temp Register 310 Load and Store InstructionsThird Dword Bit A1 Bit A0 Number of Bytes Allowed to Load and StoreReserved 2726 No Flush Store instruction only IT20 Instruction Type 3129DSA Relative Bit Source DestinationThis bit has no effect unless the Prefetch Enable bit DMA Control Dcntl register is setScsi Scripts Instruction Set Chapter Electrical Specifications DC CharacteristicsOperating Conditions1 Symbol Parameter Min Max Unit Test ConditionsAbsolute Maximum Stress Ratings1 Input CapacitanceBidirectional Signals-MAD70, MAS/10, MCE/, MOE/, MWE Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER/, GPIO24Output Signal-TDO TolerANT Technology Electrical Characteristics Output Signals-IRQ/, MAC/TESTOUT, REQOutput Signal-SERR Symbol Parameter Min1 Max Unit Test Conditions PqfpRise and Fall Time Test Condition Input Current as a Function of Input Voltage AC Characteristics Symbol Parameter Min Max Unit12 External Clock1 Reset Input Interrupt OutputPCI and External Memory Interface Timing Diagrams Electrical Specifications 15 PCI Configuration Register Read PCI Configuration Register ReadTarget Timing 16 PCI Configuration Register Write 10 PCI Configuration Register Write17 32-Bit Operating Register/SCRIPTS RAM Read 11 32-Bit Operating Register/SCRIPTS RAM Read18 64-Bit Address Operating Register/SCRIPTS RAM Read 12 64-Bit Address Operating Register/SCRIPTS RAM Read19 32-Bit Operating Register/SCRIPTS RAM Write 13 32-Bit Operating Register/SCRIPTS RAM Write20 64-Bit Address Operating Register/SCRIPTS RAM Write 14 64-Bit Address Operating Register/SCRIPTS RAM WriteInitiator Timing 21 Nonburst Opcode Fetch, 32-Bit Address and Data15 Nonburst Opcode Fetch, 32-Bit Address and Data 22 Burst Opcode Fetch, 32-Bit Address and Data 16 Burst Opcode Fetch, 32-Bit Address and Data 23 Back-to-Back Read, 32-Bit Address and Data 17 Back-to-Back Read, 32-Bit Address and Data 24 Back-to-Back Write, 32-Bit Address and Data 18 Back-to-Back Write, 32-Bit Address and Data 25 Burst Read, 32-Bit Address and Data 19 Burst Read, 32-Bit Address and Data 26 Burst Read, 64-Bit Address and Data 20 Burst Read, 64-Bit Address and Data 27 Burst Write, 32-Bit Address and Data 21 Burst Write, 32-Bit Address and Data 28 Burst Write, 64-Bit Address and 32-Bit Data 22 Burst Write, 64-Bit Address and 32-Bit Data External Memory Timing 29 External Memory Read23 External Memory Read STOP/ Driven by LSI53C875A 30 External Memory Write External Memory Write timings start on 24 External Memory Write Data Byte Enable Address out from MOE/, MCE/ High Driven by LSI53C875A Higher Valid Write Data CBE30 Byte Enable Data Byte Enable Out Lower Address Data LSI53C875A-Data Data Byte Enable Data Out Symbol Parameter Min Slow Memory ≤ 128 Kbytes Read CycleSlow Memory ≤ 128 Kbytes Write Cycle 30 Slow Memory ≤ 128 Kbytes Write Cycle≤ 64 Kbytes ROM Read Cycle ≤ 64 Kbyte ROM Write Cycle 32 ≤ 64 Kbyte ROM Write CycleScsi Timing Diagrams 37 Initiator Asynchronous Send38 Initiator Asynchronous Receive 34 Initiator Asynchronous Receive39 Target Asynchronous Send 35 Target Asynchronous Send40 Target Asynchronous Receive 41 SCSI-1 Transfers 5.0 MbytesSymbol Parameter Min Max Unit 37 Initiator and Target Synchronous Transfer Package Diagrams 38 LSI53C875A 160-Pin Pqfp Mechanical DrawingPin Pqfp P3 Mechanical Drawing Sheet 2 Signal Pin 44 160 Pqfp Pin List by LocationPin BGA Mechanical Drawing 45 169 BGA Pin List by Location NC1Appendix a Register Summary Table A.2 LSI53C875A Scsi Register Map Register Summary Scratch Registers C-RSCRATCHC-SCRATCHR Table A.2 LSI53C875A Scsi Register Map Register Summary Appendix B External Memory Interface Diagram Examples Figure B.2 64 Kbyte Interface with 150 ns Memory External Memory Interface Diagram Examples Figure B.4 512 Kbyte Interface with 150 ns Memory Symbols IndexIX-2Index Numerics SGE 4-74,4-77 SIIX-4Index IX-5 IX-6Index IX-7 IX-8Index IX-9 IX-10Index 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