LSI 53C875A technical manual External Memory Timing, External Memory Read

6.4.3 External Memory Timing

The tables and figures in this section describe LSI53C875A external timings. The External Memory Write timings start on page 6-40.

Table 6.29 External Memory Read

Symbol	Parameter	Min	Max	Unit
t1	Shared signal input setup time	7	–	ns
t2	Shared signal input hold time	0	–	ns
t3	CLK to shared signal output valid	–	11	ns
t11	Address setup to MAS/ HIGH	25	–	ns
t12	Address hold from MAS/ HIGH	15	–	ns
t13	MAS/ pulse width	25	–	ns
t14	MCE/ LOW to data clocked in	150	–	ns
t15	Address valid to data clocked in	205	–	ns
t16	MOE/ LOW to data clocked in	100	–	ns
t17	Data hold from address, MOE/, MCE/ change	0	–	ns
t19	Data setup to CLK HIGH	5	–	ns

PCI and External Memory Interface Timing Diagrams 6-35