Figure 6.28 Normal/Fast Memory (128 Kbytes) Multiple Byte Access Write Cycle (Cont.)

CLK (Driven by System)

FRAME/ (Driven by Master)

AD (Driven by Master-Addr; LSI53C875A-Data)

C_BE[3:0]/ (Driven by Master)

PAR (Driven by Master-Addr;

LSI53C875A-Data)

IRDY/ (Driven by Master)

TRDY/ (Driven by LSI53C875A)

STOP/ (Driven by LSI53C875A)

DEVSEL/ (Driven by LSI53C875A)

MAD (Driven by LSI53C875A;

MAS1/ (Driven by LSI53C875A)

MAS0/ (Driven by LSI53C875A)

MCE/ (Driven by LSI53C875A)

MOE/ (Driven by LSI53C875A)

MWE/ (Driven by LSI53C875A)

15

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28

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32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data In

Byte Enable

In

Data Out

Lower

Data Out

Address

 

 

PCI and External Memory Interface Timing Diagrams

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LSI 53C875A technical manual Data Byte Enable Data Out