Figure 2.3 DMA FIFO Sections

8 Bytes Wide

.

.

.

118

Transfers

Deep

.

.

.

8Bits

Byte Lane 7

8Bits

Byte Lane 6

8 Bits

8 Bits

8 Bits

8 Bits

8 Bits

Byte Lane 5

Byte Lane 4

Byte Lane 3

Byte Lane 2

Byte Lane 1

 

 

 

 

 

8Bits

Byte Lane 0

The LSI53C875A automatically supports misaligned DMA transfers. A 944-byte FIFO allows the LSI53C875A to support 2, 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface.

2.2.12.1 Data Paths

The data path through the LSI53C875A is dependent on whether data is being moved into or out of the chip, and whether SCSI data is being transferred asynchronously or synchronously.

Figure 2.4 shows how data is moved to/from the SCSI bus in each of the different modes.

2-28

Functional Description

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LSI 53C875A technical manual DMA Fifo Sections, Data Paths