Residual data in the synchronous data FIFO – a transfer other than synchronous data receive is started with data left in the synchronous data FIFO.

UDC

Unexpected Disconnect

2

 

This bit is set when the LSI53C875A is operating in the

 

initiator mode and the target device unexpectedly

 

 

disconnects from the SCSI bus. This bit is only valid

 

 

when the LSI53C875A operates in the initiator mode.

 

 

When the LSI53C875A operates in low level mode, any

 

disconnect causes an interrupt, even a valid SCSI

 

 

disconnect. This bit is also set if a selection time-out

 

 

occurs (it may occur before, at the same time, or stacked

 

after the STO interrupt, since this is not considered an

 

 

expected disconnect).

 

RST

SCSI RST/ Received

1

 

This bit is set when the LSI53C875A detects an active

 

 

SRST/ signal, whether the reset is generated external to

 

the chip or caused by the Assert RST bit in the SCSI

 

 

Control One (SCNTL1) register. This SCSI reset

 

 

detection logic is edge-sensitive, so that multiple

 

 

interrupts are not generated for a single assertion of the

 

SRST/ signal.

 

PAR

Parity Error

0

 

This bit is set when the LSI53C875A detects a parity

 

 

error while receiving SCSI data. The Enable Parity

 

 

Checking bit (bit 3 in the SCSI Control Zero (SCNTL0)

 

 

register) must be set for this bit to become active. The

 

LSI53C875A always generates parity when sending SCSI data.

Register: 0x43

SCSI Interrupt Status One (SIST1)

Read Only

7

 

 

 

3

2

1

0

 

 

R

 

 

STO

GEN

HTH

x

x

x

x

x

0

0

0

 

 

 

 

 

 

 

 

Reading the SIST1 register returns the status of the various interrupt conditions, whether they are enabled in the SCSI Interrupt Enable One

4-78Registers

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LSI 53C875A technical manual Scsi RST/ Received, Parity Error, Scsi Interrupt Status One SIST1 Read Only