C e m b e r 2 0 0
Technical Manual
Trademark Acknowledgment
Organization
Audience
Ansi
Conventions Used in This Manual
PCI Special Interest Group
Revision Record
Revision Date Remarks
ViPreface
Contents
Chapter Signal Descriptions
Chapter Registers
Figures
Contents
Tables
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR
XivContents
Chapter General Description
Typical LSI53C875A System Application
Benefits of Ultra Scsi
New Features in the LSI53C875A
LSI53C875A Benefits Summary
TolerANT Technology
Scsi Performance
Integration
PCI Performance
Ease of Use
Scripts RAM
Flexibility
Testability
Reliability
Chapter Functional Description
PCI Addressing
PCI Functional Description
Configuration Space
PCI Bus Commands and Functions Supported
Interrupt Acknowledge Command
PCI Bus Commands and Encoding Types for the LSI53C875A
Special Cycle Command
CBE30 Command Type Supported as Master Supported as Slave
2.4 I/O Write Command
2.3 I/O Read Command
Reserved Command
Memory Read Command
Dual Address Cycle DAC Command
Memory Read Multiple Command
Memory Read Line Command
PCI Functional Description
Memory Write and Invalidate Command
PCI Cache Mode
Issuing Cache Commands
Enabling Cache Mode
Memory Write Caching
Memory Read Caching
Host Memory
PCI Cache Mode Alignment
Read Example
Examples
Write Example
Write Example
Memory-to-Memory Moves
Scsi Functional Description
Scripts Processor
Phase Mismatch Handling in Scripts
Internal Scripts RAM
Hardware Control of Scsi Activity LED
3 64-Bit Addressing in Scripts
Designing an Ultra Scsi System
Using the Scsi Clock Quadrupler
Prefetching Scripts Instructions
Load and Store Instructions
Opcode Fetch Burst Capability
Scsi Loopback Mode
Jtag Boundary Scan Testing
Parity Options
Bit Name Location Description
Bits Used for Parity Control and Generation
Scsi Parity Control
Scsi Parity Errors and Interrupts
Parity Checking/Generation
DMA Fifo
Data Paths
DMA Fifo Sections
Asynchronous Scsi Send
LSI53C875A Host Interface Scsi Data Paths
Synchronous Scsi Send
Synchronous Scsi Receive
Asynchronous Scsi Receive
Scsi Termination
Scsi Bus Interface
Regulated Termination for Ultra Scsi
Select/Reselect During Selection/Reselection
Determining the Data Transfer Rate
Synchronous Operation
Determining the Synchronous Transfer Rate
Scsi Control Three SCNTL3 Register, Bits 20 CCF20
Scsi Control Three SCNTL3 Register, Bits 64 SCF20
Scsi Transfer Sxfer Register, Bits 75 TP20
Ultra Scsi Synchronous Data Transfers
Polling and Hardware Interrupts
Interrupt Handling
Registers
Functional Description
Fatal vs. Nonfatal Interrupts
Masking
Stacked Interrupts
Halting in an Orderly Fashion
Read Interrupt Status Zero ISTAT0
Sample Interrupt Service Routine
Chained Block Moves
Wide Scsi Send Bit
Block Move and Chained Block Move Instructions
Swide Register
Wide Scsi Receive Bit
Sodl Register
Chained Block Move Scripts Instruction
Parallel ROM Interface
MAD31 Available Memory Space
Parallel ROM Support
Serial Eeprom Interface
Default Download Mode
No Download Mode
Power Management
Mode a Serial Eeprom Data Format
Byte Name Description
Power State D1
Power State D0
Power States
Configuration Register Bits
Power State D3
Power State D2
Functional Description
Chapter Signal Descriptions
LSI53C875A Functional Signal Grouping
LSI53C875A Functional Signal Grouping
Internal Pull-ups on LSI53C875A Signals
Signal Descriptions
Signal Name Pull-up Current Conditions for Pull-up
LSI53C875A Internal Pull-ups
System Signals
PCI Bus Interface Signals
System Signals
Type Strength Description
Address and Data Signals
Address and Data Signals
Bus Command and Byte Enables are
Interface Control Signals
Interface Control Signals
Initialization Device Select is used as a chip select
Error Reporting Signals
Arbitration Signals
Arbitration Signals
Error Reporting Signals
Interrupt Signal
Scsi Bus Interface Signals
Scsi Bus Interface Signal
Interrupt Signal
Scsi Control Signals
Scsi Signals
Scsi Signals
10 Scsi Control Signals
11 Gpio Signals
Gpio Signals
Scsi General Purpose I/O pin. Optionally
Scsi General Purpose I/O pin. This pin
12 ROM Flash and Memory Interface Signals
ROM Flash and Memory Interface Signals
13 Test Interface Signals
Test Interface Signals
Memory Address/Data Bus. This bus is used
14 Power and Ground Signals
Power and Ground Signals
MAD Bus Programming
15 Decode of MAD Pins
MAD Bus Programming
Signal Descriptions
Chapter Registers
PCI Configuration Registers
Vendor ID Read Only
Registers
VIDVendor ID150
Enable Parity Error Response
Command Read/Write
Device ID Read Only
DIDDevice ID150
EBM
WIE
EMS
EIS
SSE
DPE
RMA
RTA
DPR
Register
Revision ID Rev ID Read Only
RIDRevision ID70
Register 0x0C
Registers 0x09-0x0B
Register 0x0E
Register 0x0D
Register 0x0F
BAR1
BAR0
Registers 0x1C-0x27
Registers 0x18-0x1B
Registers 0x28-0x2B
Registers 0x2C-0x2D
Subsystem ID Read Only
Registers 0x2E-0x2F
SID
Subsystem ID 150
Erba
Expansion ROM Base Address Read/Write
Expansion ROM Base Address 310
Register 0x3C
Registers 0x35-0x3B
Capabilities Pointer Read Only CPCapabilities Pointer70
Interrupt Line Read/Write ILInterrupt Line70
Register 0x3E
Register 0x3D
Register 0x3F
MGMINGNT70
Pmes
D1S
D2S
DSI
APS
Dslt
Dscl
PEN
Bridge Support Extensions Pmcsrbse Read Only
Data Read Only
Scsi Registers
DATAData70
Scsi Register Address Map
Arbitration Mode
ARB10 Arbitration Mode Bits 1
Scsi Control Zero SCNTL0 Read/Write
Simple Arbitration
Start Start Sequence5
Full Arbitration, Selection/Reselection
EPC
Watn
AAP
ADB
EXC
DHP
RST
CON
Aesp
Iarb
SSTStart Scsi Transfer0
Scsi Control Two SCNTL2 Read/Write
Chained Mode
SDU
Scsi Disconnect Unexpected
Slphben
Slpmd
WSS
VUE0
WSRWide Scsi Receive0
Ultra Scsi Enable
Scsi Control Three SCNTL3 Read/Write
USE
SCF20 Synchronous Clock Conversion Factor
Enable Wide Scsi
EWS
CCF20 Clock Conversion Factor
SRE
RRE
ENC
TP20 Scsi Synchronous Transfer Period
Scsi Transfer Sxfer Read/Write
Transfer Rate
Synch CLK MHz
Bits Period ns Mbytes/s
MO40 Max Scsi Synchronous Offset
Synchronous Offset
Maximum Synchronous Offset
Encoded Destination Scsi ID
Scsi Destination ID Sdid Read/Write
General Purpose GPREG0 Read/Write
Gpio
Sfbr Scsi First Byte Received70
Scsi First Byte Received Sfbr Read/Write
ACK
REQ
BSY
SEL
Register 0x0B
Register 0x0A
VAL
Enid
SACK/ Status
SREQ/ Status
SBSY/ Status
SSEL/ Status
Abrt
Mdpe
SSI
SIR
Scsi Registers
ORF
ILF
OLF
LOA
AIP
WOA
Bytes or Words
Scsi Synchronous Data Fifo Word Count
SSTAT2 bit
SDP0L
ORF1
ILF1
OLF1
Ldsc
SPL1
SDP1
DSA
Interrupt Status Zero ISTAT0 Read/Write
Srst Software Reset6
Abort Operation
Sigp
Signal Process
SEM
Semaphore
Dipdma Interrupt Pending0
Sipscsi Interrupt Pending1
Srun
Flsh
Syncirqd
MBOX0 Mailbox Zero70
Mailbox Zero MBOX0 Read/Write
Mailbox One MBOX1 Read/Write
MBOX1 Mailbox One70
FMTByte Empty in DMA FIFO70
Chip Test Zero CTEST0 Read/Write
Chip Test One CTEST1 Read Only
FFLByte Full in DMA FIFO70
Ddir
Register 0x1A
CIO
Dreq
Teop
Dack
FLF
Register 0x1B
CLF
Temp
Registers 0x1C-0x1F
DMA Fifo Dfifo
58Registers
FBL3
Bdis
ZSD
Srtm
Chip Test Five CTEST5 Read/Write
FBL20 Fifo Byte Control
Adck
Clock Address Incrementor
DFS
Bbck
Masr
BL2
DBC
Dfdma FIFO70
Dcmd DMA Command70
DMA Command Dcmd Read/Write
Dnad
Registers 0x2C-0x2F
DSP
Dsps DMA Scripts Pointer Save310
DMA Scripts Pointer Save Dsps Read/Write
Scratch Register a Scratcha Read/Write
Scratcha Scratch Register a 310
BL10 Burst Length
DMA Mode Dmode Read/Write
Destination I/O Memory Enable
Source I/O Memory Enable
ERLEnable Read Line3
Siom
Burst Opcode Fetch Enable
Enable Read Multiple
Ermp
BOF
Master Data Parity Error Bus Fault
DMA Interrupt Enable Dien Read/Write
Scripts Interrupt Instruction Received Reserved
Illegal Instruction Detected
Register 0x3B
Register 0x3A
Clse
PFF
SSM
Single Step Mode
Irqmirq Mode3
STDStart DMA Operation2
IRQ Disable
Irqd
COMLSI53C700 Compatibility0
0x40
Registers 0x3C-0x3F
Adder
RSL
CMP
SGE
UDC
GEN
STO
Initiator Mode Phase Mismatch Target Mode SATN/ Active
HTHHandshake-to-Handshake Timer Expired0
Scsi Interrupt Status Zero SIST0 Read Only
This bit is set when an arbitration only or full arbitration
Scsi RST/ Received
Parity Error
PAR
Scsi Interrupt Status One SIST1 Read Only
HTH
Handshake-to-Handshake Timer Expired
Scsi Longitudinal Parity Slpar Read/Write
Slpar Scsi Longitudinal Parity70
Data Bytes Running Slpar
Scsi Wide Residue Swide Read/Write
Memory Access Control Macntl Read/Write
Swide Scsi Wide Residue70
TYP
DRD
DWR
Pscpt
Scpts Scripts
Gpiogpio Enable10
Gpio Enable
Scsi Timer Zero STIME0 Read/Write
HTH30 Handshake-to-HandshakeTimer Period
SEL30 Selection Time-Out30
Gensf
Hthba
Hthsf
Register 0x4B
Register 0x4A
Ssaid
Register 0x4C
SLT
ART
Sclk
Register 0x4D
ISO
QEN
Qsel
Register 0x4E
SCE
ROF
AWS
SZM
EXT
LOW
STR
Register 0x4F
Timer Test Mode
Disable Single Initiator Response
S16 Bit System
TTM
Scsi Input Data Latch Sidl Read Only
STW
Sidlscsi Input Data Latch150
Lock
Register 0x53
Chip Control 0 CCNTL0 Read/Write
Enable Phase Mismatch Jump
Enpmj
Pmjctl Jump Control6
Disfc
Enndj
Dils
Ddac
Zmode
64TIMOD
EN64TIBMV
Enable 64-Bit Direct Bmov
EN64DBMV
Scsi Bus Data Lines Sbdl Read Only
Register 0x5A-0x5B
64-Bit Scripts Selectors
Registers 0x5C-0x5F
Registers 0x60-0x9F
Memory Move Read Selector Mmrs Read/Write
Registers 0xA0-0xA3
Mmrs
Memory Move Read Selector Mmrs
Registers 0xA8-0xAB
Registers 0xA4-0xA7
Mmws
SFS
Registers 0xB0-0xB3
Registers 0xAC-0xAF
DRS
Sbms
Registers 0xB4-0xB7
Phase Mismatch Jump Registers
Registers 0xB8-0xBB
Registers 0xBC-0xBF
Registers 0xC4-0xC7
Registers 0xC0-0xC3
PMJAD1
PMJAD2
Registers 0xCC-0xCF
Registers 0xC8-0xCB
RBC
Entry Storage Address ESA Read/Write
Registers 0xD0-0xD3
ESA
Entry Storage Address 310
Registers 0xD8-0xDA
Registers 0xD4-0xD7
SBC
Registers 0xDC-0xDF
Register 0xDB
Registers 0xE0-0xFF
Csbc
Scsi Scripts
Low Level Register Interface Mode
High Level Scsi Scripts Mode
Scripts Instructions
Sample Operation
Instruction Description
Scsi Scripts Instruction Set
Scripts Overview
First Dword
Block Move Instruction
TIA
Direct Addressing
Table Indirect Bit Addressing
Command Not Used Don’t Care
OPCOpCode27
Target Mode
OPC Instruction Defined
Initiator Mode
SCSIP20 Scsi Phase2624
Scsi Phase
Scsi Information Transfer Phase
TC230 Transfer Counter230
I/O Instruction
Target Mode Initiator Mode
Second Dword
Start Address 310
OPC20 OpCode 2927
IT10 Instruction Type I/O Instruction 3130
Reselect Instruction
Instruction Defined
Wait Select Instruction
Disconnect Instruction
Set Instruction
Clear Instruction
Select Instruction
Wait Reselect Instruction
Wait Disconnect Instruction
TITable Indirect Mode25
Relative Addressing Mode
Table Indirect
Direct
Relative
Bit
Table Relative
Command Table Offset Absolute Jump Offset
Set/Clear Satn
Set/Clear Sack Reserved
IT10 Instruction Type Read/Write Instruction 3130
Read/Write Instructions
O20 Operator 2624
Use data8/SFBR
A60 Register Address A60 2216
Read-Modify-Write Cycles
Read/Write Instructions
Move To/From Sfbr Cycles
Transfer Control Instructions
Transfer Control Instructions
IT10 Instruction Type Transfer Control 3130
Jump Instruction
Return Instruction
Call Instruction
Interrupt-on-the-Fly Instruction
Interrupt Instruction
RARelative Addressing Mode23
Scsi Phase Comparisons
Jump/Call an Absolute Address
Jump/Call a Relative Address
JMP
Bit 2 is asserted
Jump If True/False
Wait for Valid Phase
Compare Phase
Compare Data
WVP
DCV
Memory Move Instructions
Data Compare Value
Jump Address 310
Reserved 2825
IT20 Instruction Type Memory Move 3129
No Flush
Dsps Register 310
Read/Write System Memory from Scripts
Third Dword
Load and Store Instructions
Temp Register 310
Bit A1 Bit A0 Number of Bytes Allowed to Load and Store
DSA Relative
IT20 Instruction Type 3129
Reserved 2726 No Flush Store instruction only
Bit Source Destination
DMA Control Dcntl register is set
This bit has no effect unless the Prefetch Enable bit
Scsi Scripts Instruction Set
DC Characteristics
Chapter Electrical Specifications
Absolute Maximum Stress Ratings1
Symbol Parameter Min Max Unit Test Conditions
Operating Conditions1
Input Capacitance
Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER/, GPIO24
Bidirectional Signals-MAD70, MAS/10, MCE/, MOE/, MWE
Output Signal-TDO
Output Signals-IRQ/, MAC/TESTOUT, REQ
TolerANT Technology Electrical Characteristics
Output Signal-SERR
Pqfp
Symbol Parameter Min1 Max Unit Test Conditions
Rise and Fall Time Test Condition
Input Current as a Function of Input Voltage
Symbol Parameter Min Max Unit
AC Characteristics
12 External Clock1
Interrupt Output
Reset Input
PCI and External Memory Interface Timing Diagrams
Electrical Specifications
PCI Configuration Register Read
15 PCI Configuration Register Read
Target Timing
10 PCI Configuration Register Write
16 PCI Configuration Register Write
11 32-Bit Operating Register/SCRIPTS RAM Read
17 32-Bit Operating Register/SCRIPTS RAM Read
12 64-Bit Address Operating Register/SCRIPTS RAM Read
18 64-Bit Address Operating Register/SCRIPTS RAM Read
13 32-Bit Operating Register/SCRIPTS RAM Write
19 32-Bit Operating Register/SCRIPTS RAM Write
14 64-Bit Address Operating Register/SCRIPTS RAM Write
20 64-Bit Address Operating Register/SCRIPTS RAM Write
21 Nonburst Opcode Fetch, 32-Bit Address and Data
Initiator Timing
15 Nonburst Opcode Fetch, 32-Bit Address and Data
22 Burst Opcode Fetch, 32-Bit Address and Data
16 Burst Opcode Fetch, 32-Bit Address and Data
23 Back-to-Back Read, 32-Bit Address and Data
17 Back-to-Back Read, 32-Bit Address and Data
24 Back-to-Back Write, 32-Bit Address and Data
18 Back-to-Back Write, 32-Bit Address and Data
25 Burst Read, 32-Bit Address and Data
19 Burst Read, 32-Bit Address and Data
26 Burst Read, 64-Bit Address and Data
20 Burst Read, 64-Bit Address and Data
27 Burst Write, 32-Bit Address and Data
21 Burst Write, 32-Bit Address and Data
28 Burst Write, 64-Bit Address and 32-Bit Data
22 Burst Write, 64-Bit Address and 32-Bit Data
29 External Memory Read
External Memory Timing
23 External Memory Read
STOP/ Driven by LSI53C875A
30 External Memory Write
External Memory Write timings start on
24 External Memory Write
Data Byte Enable
Address out from MOE/, MCE/ High
Driven by LSI53C875A Higher Valid Write Data
CBE30 Byte Enable
Data Byte Enable Out Lower Address
Data LSI53C875A-Data
Data Byte Enable Data Out
Slow Memory ≤ 128 Kbytes Read Cycle
Symbol Parameter Min
30 Slow Memory ≤ 128 Kbytes Write Cycle
Slow Memory ≤ 128 Kbytes Write Cycle
≤ 64 Kbytes ROM Read Cycle
32 ≤ 64 Kbyte ROM Write Cycle
≤ 64 Kbyte ROM Write Cycle
37 Initiator Asynchronous Send
Scsi Timing Diagrams
34 Initiator Asynchronous Receive
38 Initiator Asynchronous Receive
35 Target Asynchronous Send
39 Target Asynchronous Send
41 SCSI-1 Transfers 5.0 Mbytes
40 Target Asynchronous Receive
Symbol Parameter Min Max Unit
37 Initiator and Target Synchronous Transfer
38 LSI53C875A 160-Pin Pqfp Mechanical Drawing
Package Diagrams
Pin Pqfp P3 Mechanical Drawing Sheet 2
44 160 Pqfp Pin List by Location
Signal Pin
Pin BGA Mechanical Drawing
NC1
45 169 BGA Pin List by Location
Appendix a Register Summary
Table A.2 LSI53C875A Scsi Register Map
Register Summary
Scratch Registers C-RSCRATCHC-SCRATCHR
Table A.2 LSI53C875A Scsi Register Map
Register Summary
Appendix B External Memory Interface Diagram Examples
Figure B.2 64 Kbyte Interface with 150 ns Memory
External Memory Interface Diagram Examples
Figure B.4 512 Kbyte Interface with 150 ns Memory
Index
Symbols
IX-2Index
SGE 4-74,4-77 SI
Numerics
IX-4Index
IX-5
IX-6Index
IX-7
IX-8Index
IX-9
IX-10Index
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