LSI 53C875A Stw, Scsi Input Data Latch Sidl Read Only, Sidlscsi Input Data Latch150

STW	SCSI FIFO Test Write			0
	Setting this bit places the SCSI core into a test mode in
	which the FIFO is easily read or written. While this bit is
	set, writes to the least significant byte of the SCSI Output
	Data Latch (SODL) register cause the entire word
	contained in the SODL to be loaded into the FIFO. These
	functions are summarized in the table below.
	Register	Register		FIFO
	Name	Operation	FIFO Bits	Function
	SODL	Write	[15:0]	Load
	SODL0	Write	[7:0]	Load
	SODL1	Write	[15:8]	None

Registers: 0x50–0x51

SCSI Input Data Latch (SIDL)

Read Only

15	0
	SIDL

x x x

x

x

x

x

x

x

x

x

x

x

x

x

x

SIDLSCSI Input Data Latch[15:0]

This register is used primarily for diagnostic testing, programmed I/O operation, or error recovery. Data received from the SCSI bus can be read from this register. Data can be written to the SCSI Output Data Latch (SODL) register and then read back into the LSI53C875A by reading this register to allow loopback testing. When receiving SCSI data, the data flows into this register and out to the host FIFO. This register differs from the SCSI Bus Data Lines (SBDL) register; SIDL contains latched data and the SBDL always contains exactly what is currently on the SCSI data bus. Reading this register causes the SCSI parity bit to be checked, and causes a parity error interrupt if the data is not valid. The power-up values are indeterminate.

SCSI Registers 4-93