Table 6.31

Normal/Fast Memory (128 Kbytes) Single Byte Access Read Cycle

 

 

 

 

 

Symbol

Parameter

Min

Max

Unit

 

 

 

 

 

t11

Address setup to MAS/ HIGH

25

ns

t12

Address hold from MAS/ HIGH

15

ns

t13

MAS/ pulse width

25

ns

t14

MCE/ LOW to data clocked in

150

ns

t15

Address valid to data clocked in

205

ns

t16

MOE/ LOW to data clocked in

100

ns

t17

Data hold from address, MOE/, MCE/ change

0

ns

t18

Address out from MOE/, MCE/ HIGH

50

ns

t19

Data setup to CLK HIGH

5

ns

Figure 6.25 Normal/Fast Memory (128 Kbytes) Single Byte Access Read Cycle

CLK

 

 

 

 

 

MAD

 

 

 

t19

 

Higher

 

 

 

 

(Addr driven by LSI53C875A;

 

1.

2.

3.

Address

Data driven by memory)

 

 

 

t11

t12

 

 

t17

 

 

 

 

 

 

 

 

MAS1/

 

 

 

 

 

(Driven by LSI53C875A)

 

 

 

 

 

 

t13

 

 

t15

 

 

 

 

 

 

MAS0/

 

 

 

 

 

(Driven by LSI53C875A)

 

 

 

 

 

 

 

 

 

t14

 

MCE/

 

 

 

 

 

(Driven by LSI53C875A)

 

 

 

 

 

 

 

 

 

t16

t18

MOE/

 

 

 

 

 

(Driven by LSI53C875A)

 

 

 

 

 

MWE/

(Driven by LSI53C875A)

1. Middle Address

2. Lower Address 3. Valid Read Data

6-42

Electrical Specifications

Page 280
Image 280
LSI 53C875A technical manual Address out from MOE/, MCE/ High