REQ

SREQ/ Status

7

ACK

SACK/ Status

6

BSY

SBSY/ Status

5

SEL

SSEL/ Status

4

ATN

SATN/ Status

3

MSG

SMSG/ Status

2

C_D

SC_D/ Status

1

I_O

SI_O/ Status

0

Register: 0x0C

DMA Status (DSTAT)

Read Only

7

6

5

4

3

2

1

0

DFE

MDPE

BF

ABRT

SSI

SIR

R

IID

1

0

0

0

0

0

x

0

 

 

 

 

 

 

 

 

Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C875A stacks interrupts). The DIP bit in the Interrupt Status Zero (ISTAT0) register is also cleared. It is possible to mask DMA interrupt conditions individually through the DMA Interrupt Enable (DIEN) register.

When performing consecutive 8-bit reads of the DSTAT, SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers (in any order), insert a delay equivalent to 12 CLK periods between the reads to ensure that the interrupts clear properly. See Chapter 2, “Functional Description”for more information on interrupts.

DFEDMA FIFO Empty7

This status bit is set when the DMA FIFO is empty. It is possible to use it to determine if any data resides in the FIFO when an error occurs and an interrupt is generated. This bit is a pure status bit and does not cause an interrupt.

SCSI Registers

4-39

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Image 131
LSI 53C875A SREQ/ Status, SACK/ Status, SBSY/ Status, SSEL/ Status, SATN/ Status, SMSG/ Status SCD/ Status SIO/ Status