LSI 53C875A technical manual DMA Fifo, Parity Checking/Generation

Figure 2.2 Parity Checking/Generation

Asynchronous

SCSI Send

PCI Interface**

X

DMA FIFO*

(64 bits X 118)

Asynchronous SCSI Receive

PCI Interface**

G

DMA FIFO*

(64 bits X 118)

Synchronous

SCSI Send

PCI Interface**

X

DMA FIFO*

(64 bits X 118)

Synchronous SCSI Receive

PCI Interface**

G

DMA FIFO* (64 bits X 118)

X

SODL Register*		SIDL Register*
	S		X
SCSI Interface**		SCSI Interface**

X = Check parity

G= Generate 32-bit even PCI parity S = Generate 8-bit odd SCSI parity

SODL Register*

SODR Register*

S

SCSI Interface**

SCSI FIFO**

(8 or 16 bits x 31)

X

SCSI Interface**

*= No parity protection

**= Parity protected

2.2.12 DMA FIFO

The DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO is illustrated in Figure 2.3. The default DMA FIFO size is 112 bytes to assure compatibility with older products in the LSI53C8XX family.

The DMA FIFO size may be set to 944 bytes by setting the DMA FIFO Size bit, bit 5, in the Chip Test Five (CTEST5) register.

SCSI Functional Description 2-27