LSI 53C875A technical manual IX-4Index

burst (Cont.)

length (BL[1:0]) 4-66length bit 2 (BL2) 4-61opcode fetch enable (BOF) 4-68size selection 2-6

bus

command and byte enables 3-5fault (BF) 4-40, 4-69

byte

count 5-37

empty in DMA FIFO (FMT) 4-53full in DMA FIFO (FFL) 4-53offset counter (BO) 4-57

C

cache line size 2-7, 2-9(CLS) 4-7

enable (CLSE) 4-70register 2-6

cache mode, see PCI cache mode 2-9call instruction 5-27

Cap_ID (CID) 4-15capabilities pointer (CP) 4-13carry test 5-30

chained block moves 2-44SCRIPTS instruction 2-47SODL register 2-46SWIDE register 2-46wide SCSI receive bit 2-46wide SCSI send bit 2-45

chained mode (CHM) 4-26change bus phases 2-17chip

control 0 (CCNTL0) 4-95control 1 (CCNTL1) 4-97revision level (V) 4-56test five (CTEST5) 4-60test one (CTEST1) 4-53test six (CTEST6) 4-62test three (CTEST3) 4-56test two (CTEST2) 4-54test zero (CTEST0) 4-53type (TYP) 4-81

CHMOV 2-44

class code (CC) 4-7

clear DMA FIFO 2-42, 4-56clear instruction 5-15, 5-17clear SCSI FIFO (CSF) 4-92CLF 2-42

CLK 3-4clock 3-4

address incrementor (ADCK) 4-60byte counter (BBCK) 4-61conversion factor (CCF[2:0]) 4-29quadrupler 2-20

CLSE 2-6, 2-7CMP 2-39compare

data 5-31phase 5-31

configuration

read command 2-5space 2-3

write command 2-5configured

as I/O (CIO) 4-54

as memory (CM) 4-54connected (CON) 4-24, 4-49CSF 2-42

CTEST4 2-25

cumulative SCSI byte count (CSBC) 4-108cycle frame 3-6

D

D1_Support (D1S) 4-16

D2_Support (D2S) 4-16DACs 2-19

data

(DATA) 4-18

acknowledge status (DACK) 4-55compare mask 5-31

compare value 5-32

parity error reported (DPR) 4-6paths 2-28

request status (DREQ) 4-55structure address (DSA) 4-47transfer direction (DDIR) 4-54

data read (DRD) 4-82data write (DWR) 4-82data_scale (DSCL) 4-17data_select (DSLT) 4-17data-in2-47

data-out2-47DCNTL 2-6,2-39decode of MAD pins 3-14default download mode 2-50destination

address 5-23

I/O memory enable (DIOM) 4-67detected parity error (from slave) (DPE) 4-5determining the data transfer rate 2-34device

ID (DID) 4-3select 3-6

specific initialization (DSI) 4-16DEVSEL/ 3-6

timing (DT[1:0]) 4-5DIEN 2-25,2-39, 2-40DIP 2-38,2-41, 2-42, 2-43direct 5-19

disable

auto FIFO clear (DISFC) 4-96dual address cycle (DDAC) 4-97

halt on parity error or ATN (target only) (DHP) 4-23internal load and store (DILS) 4-96

single initiator response (DSI) 4-92disconnect 2-17

disconnect instruction 5-15

DMA

byte counter (DBC) 4-62command (DCMD) 4-63control (DCNTL) 4-70direction (DDIR) 4-61FIFO 2-8, 2-27, 2-38

(DF) 4-62(DFIFO) 4-57

byte offset counter, bits [9:8] (BO[9:8]) 4-62empty (DFE) 4-39

size (DFS) 4-61interrupt 2-39, 2-40, 2-42

enable (DIEN) 4-69

IX-4Index