Note:

This bit has no effect unless the Prefetch Enable bit in the

 

 

DMA Control (DCNTL) register is set.

 

LS

Load and Store

24

 

 

When this bit is set, the instruction is a Load. When

 

 

cleared, it is a Store.

 

R

Reserved

23

RA[6:0]

Register Address

[22:16]

 

 

A[6:0] selects the register to Load and Store to/from

 

 

within the LSI53C875A.

 

R

Reserved

[15:3]

BC

Byte Count

[2:0]

 

 

This value is the number of bytes to Load and Store.

5.8.2 Second Dword

 

 

 

 

31

 

 

 

 

0

 

 

 

 

 

DMA SCRIPTS Pointer Save (DSPS) Register - Memory I/O Address/DSA Offset

 

 

 

 

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

 

 

 

 

 

 

 

 

Memory I/O Address / DSA Offset

[31:0]

 

 

This is the actual memory location of where to Load and

 

 

Store, or the offset from the Data Structure Address

 

 

(DSA) register value.

 

Load and Store Instructions

5-37

Page 237
Image 237
LSI 53C875A technical manual This bit has no effect unless the Prefetch Enable bit, DMA Control Dcntl register is set