Appendix A

Register Summary

Table A.1

LSI53C875A PCI Register Map

 

 

 

 

 

 

 

Register Name

Address

Read/Write

Page

 

 

 

 

Base Address Register One (MEMORY)

0x14–0x17

Read/Write

4-9

 

 

 

 

Base Address Register Two (SCRIPTS RAM)

0x18–0x1B

Read/Write

4-10

 

 

 

 

Base Address Register Zero (I/O)

0x10–0x13

Read/Write

4-9

 

 

 

 

Bridge Support Extensions (PMCSR_BSE)

0x46

Read Only

4-17

 

 

 

 

Cache Line Size

0x0C

Read/Write

4-7

 

 

 

 

Capabilities Pointer

0x34

Read Only

4-13

 

 

 

 

 

Capability ID

 

0x40

Read Only

4-15

 

 

 

 

 

Class Code

 

0x09–0x0B

Read Only

4-7

 

 

 

 

 

Command

 

0x04–0x05

Read/Write

4-3

 

 

 

 

 

Data

 

0x47

Read Only

4-18

 

 

 

 

 

Device ID

 

0x02–0x03

Read Only

4-3

 

 

 

 

Expansion ROM Base Address

0x30–0x33

Read/Write

4-12

 

 

 

 

 

Header Type

 

0x0E

Read Only

4-8

 

 

 

 

 

Interrupt Line

 

0x3C

Read/Write

4-13

 

 

 

 

 

Interrupt Pin

 

0x3D

Read Only

4-14

 

 

 

 

Latency Timer

0x0D

Read/Write

4-8

 

 

 

 

 

Max_Lat

 

0x3F

Read Only

4-14

 

 

 

 

 

Min_Gnt

 

0x3E

Read Only

4-14

 

 

 

 

Next Item Pointer

0x41

Read Only

4-15

 

 

 

 

 

LSI53C875A PCI to Ultra SCSI Controller

A-1

Page 301
Image 301
LSI 53C875A technical manual Appendix a Register Summary