Memory Read Multiple Command | LSI 53C875A specs

2.1.2.10 Memory Read Multiple Command

This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C875A supports PCI Memory Read Multiple functionality and issues Memory Read Multiple commands on the PCI bus when the Read Multiple Mode is enabled. This mode is enabled by setting bit 2 (ERMP) of the DMA Mode (DMODE) register. If cache mode is enabled, a Memory Read Multiple command is issued on all read cycles, except opcode fetches, when the following conditions are met:

•The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL) register) and the ERMP bit (Enable Read Multiple, bit 2, DMA Mode (DMODE) register) are set.

•The Cache Line Size register for each function contains a legal burst size value (2, 4, 8, 16, 32, or 64) and that value is less than or equal to the DMODE burst size.

•The transfer will cross a cache line boundary.

When these conditions are met, the chip issues a Memory Read Multiple command instead of a Memory Read during all PCI read cycles.

Burst Size Selection – The Read Multiple command reads in multiple cache lines of data in a single bus ownership. The number of cache lines to read is a multiple of the cache line size specified in Revision 2.2 of the PCI specification. The logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size determined from the DMA Mode (DMODE) burst size bits, and the Chip Test Five (CTEST5), bit 2.

2.1.2.11 Dual Address Cycle (DAC) Command

The LSI53C875A performs DACs when 64-bit addressing is required. Refer to the PCI 2.2 specification. If any of the selector registers contain a nonzero value, a DAC is generated. See 64-bit SCRIPTS Selectors in Chapter 4, “Registers,”for additional information.

2.1.2.12 Memory Read Line Command

This command is identical to the Memory Read command, except that it additionally indicates that the master intends to fetch a complete cache

2-6	Functional Description

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LSI 53C875A technical manual Memory Read Multiple Command, Dual Address Cycle DAC Command, Memory Read Line Command

Contents

Technical Manual C e m b e r 2 0 0 Trademark Acknowledgment Audience Organization Ansi PCI Special Interest Group Conventions Used in This ManualRevision Record Revision Date Remarks ViPreface Contents Chapter Signal Descriptions Chapter Registers Figures Contents Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR XivContents Chapter General Description Typical LSI53C875A System Application New Features in the LSI53C875A Benefits of Ultra Scsi TolerANT Technology LSI53C875A Benefits Summary Scsi Performance Integration PCI PerformanceEase of Use Flexibility Scripts RAM Reliability Testability Chapter Functional Description PCI Functional Description PCI Addressing PCI Bus Commands and Functions Supported Configuration Space PCI Bus Commands and Encoding Types for the LSI53C875A Interrupt Acknowledge CommandSpecial Cycle Command CBE30 Command Type Supported as Master Supported as Slave 2.3 I/O Read Command 2.4 I/O Write CommandReserved Command Memory Read Command Dual Address Cycle DAC Command Memory Read Multiple CommandMemory Read Line Command PCI Functional Description Memory Write and Invalidate Command PCI Cache Mode Enabling Cache Mode Issuing Cache Commands Memory Read Caching Memory Write Caching PCI Cache Mode Alignment Host Memory Examples Read Example Write Example Write Example Scsi Functional Description Memory-to-Memory Moves Phase Mismatch Handling in Scripts Scripts Processor Internal Scripts RAM 3 64-Bit Addressing in Scripts Hardware Control of Scsi Activity LED Using the Scsi Clock Quadrupler Designing an Ultra Scsi System Prefetching Scripts Instructions Opcode Fetch Burst Capability Load and Store Instructions Jtag Boundary Scan Testing Scsi Loopback Mode Parity Options Bits Used for Parity Control and Generation Bit Name Location Description Scsi Parity Errors and Interrupts Scsi Parity Control DMA Fifo Parity Checking/Generation DMA Fifo Sections Data Paths LSI53C875A Host Interface Scsi Data Paths Asynchronous Scsi Send Synchronous Scsi Send Asynchronous Scsi Receive Synchronous Scsi Receive Scsi Bus Interface Scsi Termination Select/Reselect During Selection/Reselection Regulated Termination for Ultra Scsi Synchronous Operation Determining the Data Transfer Rate Determining the Synchronous Transfer Rate Scsi Control Three SCNTL3 Register, Bits 64 SCF20 Scsi Control Three SCNTL3 Register, Bits 20 CCF20Scsi Transfer Sxfer Register, Bits 75 TP20 Ultra Scsi Synchronous Data Transfers Polling and Hardware Interrupts Interrupt HandlingRegisters Functional Description Fatal vs. Nonfatal Interrupts Masking Stacked Interrupts Halting in an Orderly Fashion Sample Interrupt Service Routine Read Interrupt Status Zero ISTAT0 Chained Block Moves Block Move and Chained Block Move Instructions Wide Scsi Send Bit Swide Register Wide Scsi Receive BitSodl Register Chained Block Move Scripts Instruction Parallel ROM Interface Parallel ROM Support MAD31 Available Memory Space Default Download Mode Serial Eeprom Interface Power Management No Download ModeMode a Serial Eeprom Data Format Byte Name Description Power State D0 Power State D1Power States Configuration Register Bits Power State D2 Power State D3 Functional Description Chapter Signal Descriptions LSI53C875A Functional Signal Grouping LSI53C875A Functional Signal Grouping Signal Descriptions Internal Pull-ups on LSI53C875A SignalsSignal Name Pull-up Current Conditions for Pull-up LSI53C875A Internal Pull-ups PCI Bus Interface Signals System SignalsSystem Signals Type Strength Description Address and Data Signals Address and Data SignalsBus Command and Byte Enables are Interface Control Signals Interface Control SignalsInitialization Device Select is used as a chip select Arbitration Signals Error Reporting SignalsArbitration Signals Error Reporting Signals Scsi Bus Interface Signals Interrupt SignalScsi Bus Interface Signal Interrupt Signal Scsi Signals Scsi Control SignalsScsi Signals 10 Scsi Control Signals Gpio Signals 11 Gpio SignalsScsi General Purpose I/O pin. Optionally Scsi General Purpose I/O pin. This pin ROM Flash and Memory Interface Signals 12 ROM Flash and Memory Interface Signals 13 Test Interface Signals Test Interface SignalsMemory Address/Data Bus. This bus is used Power and Ground Signals 14 Power and Ground Signals 15 Decode of MAD Pins MAD Bus Programming MAD Bus Programming Signal Descriptions PCI Configuration Registers Chapter Registers Vendor ID Read Only RegistersVIDVendor ID150 Command Read/Write Enable Parity Error ResponseDevice ID Read Only DIDDevice ID150 WIE EBMEMS EIS DPE SSERMA RTA Register DPRRevision ID Rev ID Read Only RIDRevision ID70 Registers 0x09-0x0B Register 0x0C Register 0x0E Register 0x0DRegister 0x0F BAR0 BAR1 Registers 0x18-0x1B Registers 0x1C-0x27Registers 0x28-0x2B Registers 0x2C-0x2D Registers 0x2E-0x2F Subsystem ID Read OnlySID Subsystem ID 150 Erba Expansion ROM Base Address Read/WriteExpansion ROM Base Address 310 Registers 0x35-0x3B Register 0x3CCapabilities Pointer Read Only CPCapabilities Pointer70 Interrupt Line Read/Write ILInterrupt Line70 Register 0x3D Register 0x3ERegister 0x3F MGMINGNT70 Pmes D2S D1SDSI APS Dscl DsltPEN Bridge Support Extensions Pmcsrbse Read Only Data Read Only Scsi RegistersDATAData70 Scsi Register Address Map ARB10 Arbitration Mode Bits 1 Arbitration ModeScsi Control Zero SCNTL0 Read/Write Simple Arbitration Full Arbitration, Selection/Reselection Start Start Sequence5 EPC WatnAAP ADB EXCDHP CON RSTAesp Iarb SSTStart Scsi Transfer0 Chained Mode Scsi Control Two SCNTL2 Read/WriteSDU Scsi Disconnect Unexpected Slpmd SlphbenWSS VUE0 Ultra Scsi Enable WSRWide Scsi Receive0Scsi Control Three SCNTL3 Read/Write USE Enable Wide Scsi SCF20 Synchronous Clock Conversion FactorEWS CCF20 Clock Conversion Factor SRE RREENC Scsi Transfer Sxfer Read/Write TP20 Scsi Synchronous Transfer Period Transfer Rate Synch CLK MHzBits Period ns Mbytes/s MO40 Max Scsi Synchronous Offset Maximum Synchronous Offset Synchronous Offset Scsi Destination ID Sdid Read/Write Encoded Destination Scsi IDGeneral Purpose GPREG0 Read/Write Gpio Scsi First Byte Received Sfbr Read/Write Sfbr Scsi First Byte Received70 REQ ACKBSY SEL Register 0x0A Register 0x0BVAL Enid SREQ/ Status SACK/ StatusSBSY/ Status SSEL/ Status Mdpe AbrtSSI SIR Scsi Registers ORF ILFOLF LOA AIPWOA Bytes or Words Scsi Synchronous Data Fifo Word CountSSTAT2 bit SDP0L ORF1 ILF1OLF1 SPL1 LdscSDP1 DSA Interrupt Status Zero ISTAT0 Read/Write Srst Software Reset6Abort Operation Signal Process SigpSEM Semaphore Sipscsi Interrupt Pending1 Dipdma Interrupt Pending0 Srun FlshSyncirqd Mailbox Zero MBOX0 Read/Write MBOX0 Mailbox Zero70Mailbox One MBOX1 Read/Write MBOX1 Mailbox One70 Chip Test Zero CTEST0 Read/Write FMTByte Empty in DMA FIFO70Chip Test One CTEST1 Read Only FFLByte Full in DMA FIFO70 Ddir Register 0x1ACIO Dreq TeopDack FLF Register 0x1BCLF Temp Registers 0x1C-0x1FDMA Fifo Dfifo 58Registers Bdis FBL3ZSD Srtm FBL20 Fifo Byte Control Chip Test Five CTEST5 Read/WriteAdck Clock Address Incrementor Bbck DFSMasr BL2 Dfdma FIFO70 DBC DMA Command Dcmd Read/Write Dcmd DMA Command70 Dnad Registers 0x2C-0x2FDSP DMA Scripts Pointer Save Dsps Read/Write Dsps DMA Scripts Pointer Save310Scratch Register a Scratcha Read/Write Scratcha Scratch Register a 310 DMA Mode Dmode Read/Write BL10 Burst Length Source I/O Memory Enable Destination I/O Memory EnableERLEnable Read Line3 Siom Enable Read Multiple Burst Opcode Fetch EnableErmp BOF DMA Interrupt Enable Dien Read/Write Master Data Parity Error Bus FaultScripts Interrupt Instruction Received Reserved Illegal Instruction Detected Register 0x3A Register 0x3BClse PFF SSM Single Step ModeIrqmirq Mode3 IRQ Disable STDStart DMA Operation2Irqd COMLSI53C700 Compatibility0 0x40 Registers 0x3C-0x3FAdder CMP RSLSGE UDC STO GEN Initiator Mode Phase Mismatch Target Mode SATN/ Active HTHHandshake-to-Handshake Timer Expired0Scsi Interrupt Status Zero SIST0 Read Only This bit is set when an arbitration only or full arbitration Parity Error Scsi RST/ ReceivedPAR Scsi Interrupt Status One SIST1 Read Only Handshake-to-Handshake Timer Expired HTHScsi Longitudinal Parity Slpar Read/Write Slpar Scsi Longitudinal Parity70 Data Bytes Running Slpar Memory Access Control Macntl Read/Write Scsi Wide Residue Swide Read/WriteSwide Scsi Wide Residue70 TYP DWR DRDPscpt Scpts Scripts Gpio Enable Gpiogpio Enable10Scsi Timer Zero STIME0 Read/Write HTH30 Handshake-to-HandshakeTimer Period SEL30 Selection Time-Out30 Gensf HthbaHthsf Register 0x4A Register 0x4B Register 0x4C SsaidSLT ART Register 0x4D SclkISO QEN Register 0x4E QselSCE ROF SZM AWSEXT LOW Register 0x4F STR Disable Single Initiator Response Timer Test ModeS16 Bit System TTM Scsi Input Data Latch Sidl Read Only STWSidlscsi Input Data Latch150 Register 0x53 Lock Enable Phase Mismatch Jump Chip Control 0 CCNTL0 Read/WriteEnpmj Pmjctl Jump Control6 Disfc EnndjDils Ddac Zmode64TIMOD Enable 64-Bit Direct Bmov EN64TIBMVEN64DBMV Scsi Bus Data Lines Sbdl Read Only 64-Bit Scripts Selectors Register 0x5A-0x5BRegisters 0x5C-0x5F Registers 0x60-0x9F Registers 0xA0-0xA3 Memory Move Read Selector Mmrs Read/WriteMmrs Memory Move Read Selector Mmrs Registers 0xA4-0xA7 Registers 0xA8-0xABMmws SFS Registers 0xAC-0xAF Registers 0xB0-0xB3DRS Sbms Phase Mismatch Jump Registers Registers 0xB4-0xB7Registers 0xB8-0xBB Registers 0xBC-0xBF Registers 0xC0-0xC3 Registers 0xC4-0xC7PMJAD1 PMJAD2 Registers 0xCC-0xCF Registers 0xC8-0xCBRBC Registers 0xD0-0xD3 Entry Storage Address ESA Read/WriteESA Entry Storage Address 310 Registers 0xD8-0xDA Registers 0xD4-0xD7SBC Register 0xDB Registers 0xDC-0xDFRegisters 0xE0-0xFF Csbc Low Level Register Interface Mode Scsi Scripts High Level Scsi Scripts Mode Scripts Instructions Sample OperationInstruction Description Scsi Scripts Instruction Set Scripts Overview Block Move Instruction First Dword TIA Direct AddressingTable Indirect Bit Addressing Command Not Used Don’t Care OPCOpCode27 Target ModeOPC Instruction Defined Initiator Mode SCSIP20 Scsi Phase2624 Scsi Phase Scsi Information Transfer PhaseTC230 Transfer Counter230 Target Mode Initiator Mode I/O InstructionSecond Dword Start Address 310 IT10 Instruction Type I/O Instruction 3130 OPC20 OpCode 2927Reselect Instruction Instruction Defined Disconnect Instruction Wait Select InstructionSet Instruction Clear Instruction Select Instruction Wait Disconnect Instruction Wait Reselect Instruction Relative Addressing Mode TITable Indirect Mode25 Direct Table IndirectRelative Bit Command Table Offset Absolute Jump Offset Table Relative Set/Clear Sack Reserved Set/Clear Satn Read/Write Instructions IT10 Instruction Type Read/Write Instruction 3130O20 Operator 2624 Use data8/SFBR Read-Modify-Write Cycles A60 Register Address A60 2216 Move To/From Sfbr Cycles Read/Write Instructions Transfer Control Instructions Transfer Control Instructions IT10 Instruction Type Transfer Control 3130Jump Instruction Call Instruction Return Instruction Interrupt Instruction Interrupt-on-the-Fly Instruction Scsi Phase Comparisons RARelative Addressing Mode23Jump/Call an Absolute Address Jump/Call a Relative Address JMP Bit 2 is assertedJump If True/False Compare Phase Wait for Valid PhaseCompare Data WVP Memory Move Instructions DCVData Compare Value Jump Address 310 Reserved 2825 IT20 Instruction Type Memory Move 3129No Flush Read/Write System Memory from Scripts Dsps Register 310 Load and Store Instructions Third DwordTemp Register 310 Bit A1 Bit A0 Number of Bytes Allowed to Load and Store IT20 Instruction Type 3129 DSA RelativeReserved 2726 No Flush Store instruction only Bit Source Destination This bit has no effect unless the Prefetch Enable bit DMA Control Dcntl register is set Scsi Scripts Instruction Set Chapter Electrical Specifications DC Characteristics Symbol Parameter Min Max Unit Test Conditions Absolute Maximum Stress Ratings1Operating Conditions1 Input Capacitance Bidirectional Signals-MAD70, MAS/10, MCE/, MOE/, MWE Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER/, GPIO24 Output Signal-TDO Output Signals-IRQ/, MAC/TESTOUT, REQ TolerANT Technology Electrical CharacteristicsOutput Signal-SERR Symbol Parameter Min1 Max Unit Test Conditions Pqfp Rise and Fall Time Test Condition Input Current as a Function of Input Voltage Symbol Parameter Min Max Unit AC Characteristics12 External Clock1 Reset Input Interrupt Output PCI and External Memory Interface Timing Diagrams Electrical Specifications PCI Configuration Register Read 15 PCI Configuration Register ReadTarget Timing 16 PCI Configuration Register Write 10 PCI Configuration Register Write 17 32-Bit Operating Register/SCRIPTS RAM Read 11 32-Bit Operating Register/SCRIPTS RAM Read 18 64-Bit Address Operating Register/SCRIPTS RAM Read 12 64-Bit Address Operating Register/SCRIPTS RAM Read 19 32-Bit Operating Register/SCRIPTS RAM Write 13 32-Bit Operating Register/SCRIPTS RAM Write 20 64-Bit Address Operating Register/SCRIPTS RAM Write 14 64-Bit Address Operating Register/SCRIPTS RAM Write Initiator Timing 21 Nonburst Opcode Fetch, 32-Bit Address and Data 15 Nonburst Opcode Fetch, 32-Bit Address and Data 22 Burst Opcode Fetch, 32-Bit Address and Data 16 Burst Opcode Fetch, 32-Bit Address and Data 23 Back-to-Back Read, 32-Bit Address and Data 17 Back-to-Back Read, 32-Bit Address and Data 24 Back-to-Back Write, 32-Bit Address and Data 18 Back-to-Back Write, 32-Bit Address and Data 25 Burst Read, 32-Bit Address and Data 19 Burst Read, 32-Bit Address and Data 26 Burst Read, 64-Bit Address and Data 20 Burst Read, 64-Bit Address and Data 27 Burst Write, 32-Bit Address and Data 21 Burst Write, 32-Bit Address and Data 28 Burst Write, 64-Bit Address and 32-Bit Data 22 Burst Write, 64-Bit Address and 32-Bit Data External Memory Timing 29 External Memory Read 23 External Memory Read STOP/ Driven by LSI53C875A 30 External Memory Write External Memory Write timings start on 24 External Memory Write Data Byte Enable Address out from MOE/, MCE/ High Driven by LSI53C875A Higher Valid Write Data CBE30 Byte Enable Data Byte Enable Out Lower Address Data LSI53C875A-Data Data Byte Enable Data Out Symbol Parameter Min Slow Memory ≤ 128 Kbytes Read Cycle Slow Memory ≤ 128 Kbytes Write Cycle 30 Slow Memory ≤ 128 Kbytes Write Cycle ≤ 64 Kbytes ROM Read Cycle ≤ 64 Kbyte ROM Write Cycle 32 ≤ 64 Kbyte ROM Write Cycle Scsi Timing Diagrams 37 Initiator Asynchronous Send 38 Initiator Asynchronous Receive 34 Initiator Asynchronous Receive 39 Target Asynchronous Send 35 Target Asynchronous Send 40 Target Asynchronous Receive 41 SCSI-1 Transfers 5.0 Mbytes Symbol Parameter Min Max Unit 37 Initiator and Target Synchronous Transfer Package Diagrams 38 LSI53C875A 160-Pin Pqfp Mechanical Drawing Pin Pqfp P3 Mechanical Drawing Sheet 2 Signal Pin 44 160 Pqfp Pin List by Location Pin BGA Mechanical Drawing 45 169 BGA Pin List by Location NC1 Appendix a Register Summary Table A.2 LSI53C875A Scsi Register Map Register Summary Scratch Registers C-RSCRATCHC-SCRATCHR Table A.2 LSI53C875A Scsi Register Map Register Summary Appendix B External Memory Interface Diagram Examples Figure B.2 64 Kbyte Interface with 150 ns Memory External Memory Interface Diagram Examples Figure B.4 512 Kbyte Interface with 150 ns Memory Symbols Index IX-2Index Numerics SGE 4-74,4-77 SI IX-4Index IX-5 IX-6Index IX-7 IX-8Index IX-9 IX-10Index Customer Feedback Reader’s Comments Excellent Good Average Fair Poor Distributors by State California New York Direct Sales Representatives by State Component and HAB Sales Offices and Design Resource Centers North America Korea International Distributors Australia Hong Kong