
EMAC Port Registers | www.ti.com |
5.8Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 50 and described in Table 44.
Figure 50. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
31 |
|
|
|
|
|
|
|
| 16 |
| Reserved |
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
15 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved
TX7 | TX6 | TX5 | TX4 | TX3 | TX2 | TX1 | TX0 |
PEND | PEND | PEND | PEND | PEND | PEND | PEND | PEND |
|
|
|
|
|
|
|
|
LEGEND: R/W = R = Read only;
Table 44. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
Bit | Field | Value | Description |
|
|
|
|
Reserved | 0 | Reserved | |
|
|
|
|
7 | TX7PEND |
| TX7PEND masked interrupt read |
|
|
|
|
6 | TX6PEND |
| TX6PEND masked interrupt read |
|
|
|
|
5 | TX5PEND |
| TX5PEND masked interrupt read |
|
|
|
|
4 | TX4PEND |
| TX4PEND masked interrupt read |
|
|
|
|
3 | TX3PEND |
| TX3PEND masked interrupt read |
|
|
|
|
2 | TX2PEND |
| TX2PEND masked interrupt read |
|
|
|
|
1 | TX1PEND |
| TX1PEND masked interrupt read |
|
|
|
|
0 | TX0PEND |
| TX0PEND masked interrupt read |
|
|
|
|
102 | C6472/TCI6486 EMAC/MDIO | SPRUEF8F |
|
| Submit Documentation Feedback |
Copyright ©