Texas Instruments TMS320TCI6486 manual Receive Interrupt Mask Clear Register Rxintmaskclear

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5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 58 and described in Table 52.

Figure 58. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

31								24
			Reserved
				R-0
23	22	21	20	19		18	17	16
RX7PULSE	RX6PULSE	RX5PULSE	RX4PULSE		RX3PULSE	RX2PULSE	RX1PULSE	RX0PULSE
MASK	MASK	MASK	MASK		MASK	MASK	MASK	MASK
15								8
			Reserved
				R-0
7	6	5	4	3		2	1	0
RX7PEND	RX6PEND	RX5PEND	RX4PEND		RX3PEND	RX2PEND	RX1PEND	RX0PEND
MASK	MASK	MASK	MASK		MASK	MASK	MASK	MASK

LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n= value after reset

Table 52. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions

Bit	Field	Value	Description
31-24	Reserved	0	Reserved; read as 0.
23	RX7PULSEMASK	0	Receive channel 7 pulse interrupt mask. Write 1 to disable interrupt.
22	RX6PULSEMASK	0	Receive channel 6 pulse interrupt mask. Write 1 to disable interrupt.
21	RX5PULSEMASK	0	Receive channel 5 pulse interrupt mask. Write 1 to disable interrupt.
20	RX4PULSEMASK	0	Receive channel 4 pulse interrupt mask. Write 1 to disable interrupt.
19	RX3PULSEMASK	0	Receive channel 3 pulse interrupt mask. Write 1 to disable interrupt.
18	RX2PULSEMASK	0	Receive channel 2 pulse interrupt mask. Write 1 to disable interrupt.
17	RX1PULSEMASK	0	Receive channel 1 pulse interrupt mask. Write 1 to disable interrupt.
16	RX0PULSEMASK	0	Receive channel 0 pulse interrupt mask. Write 1 to disable interrupt.
15-8	Reserved	0	Reserved; read as 0.
7	RX7PENDMASK	0	Receive channel 7 pending interrupt mask. Write 1 to disable interrupt.
6	RX6PENDMASK	0	Receive channel 6 pending interrupt mask. Write 1 to disable interrupt.
5	RX5PENDMASK	0	Receive channel 5 pending interrupt mask. Write 1 to disable interrupt.
4	RX4PENDMASK	0	Receive channel 4 pending interrupt mask. Write 1 to disable interrupt.
3	RX3PENDMASK	0	Receive channel 3 pending interrupt mask. Write 1 to disable interrupt.
2	RX2PENDMASK	0	Receive channel 2 pending interrupt mask. Write 1 to disable interrupt.
1	RX1PENDMASK	0	Receive channel 1 pending interrupt mask. Write 1 to disable interrupt.
0	RX0PENDMASK	0	Receive channel 0 pending interrupt mask. Write 1 to disable interrupt.

110	C6472/TCI6486 EMAC/MDIO	SPRUEF8F –March 2006 –Revised November 2010
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