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Texas Instruments TMS320TCI6486 manual Divide-by-N State Machine DSM, DSM State Transition Diagram

Models: TMS320TCI6486

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EMAC Functional Architecture

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2.7.3Divide-by-N State Machine (DSM)

The divide-by-N state machine fully implements the functionality of the count-based interrupt pacing. The CNT_CFG bit field of the TPCFG and RPCFG registers (described in Section 3) is set to 0 on reset and immediately generates a pulse (basically means a zero delay), when the TIME_CFG is also set to 0 (i.e., timed-delay SM is disabled). When the TIME_CFG is set to non-zero, it then disables the divide-by-N state machine. When the CNT_CFG is set to non-zero, the CNT_CFG number of events are counted before an output pulse is generated. The counter resets (and reloads) every time when a divide-by-N pulse is generated.

The state machine has three states, WAITING, COUNT, and OUTPUT. Upon reset, the state machine is placed in the WAITING state. The state machine makes transitions between the states as shown in Figure 17. Note that states that are grayed out are transitional states, in the sense that the SM does not stay in the grayed state. While in the transitional state, it typically does an operation, like setting the counter to a certain value.

Figure 17. DSM State Transition Diagram

EVT_PULSE=0(or)EVT_PULSE=1&&

CNT >=CNT_CFG&& TIME_CFGI=0

						>=
				&&	CNT CFG==0			PULSE=0	CR=1
				&&		_		PULSE=0	CR=1
	PULSE=1			TIME			_	&&
			&&				EVT	&&
		CFG					EVT

EVT	_
EVT		_
CNT						EVT_PULSE=0

&&CR=0

					Waiting
		PULSE=1			&&	&&	Increment
					CFG	&&	Increment
					CFG		CNT
							CNT
EVT	_			CNT
EVT			<	CR=0
CNT

			EVT
			CNT
EVT				_
EVT				>=
CNT				PULSE=0
_				CFG
	PULSE=1			CFG
<				CNT
CNT				_	(or)
CNT					(or)
		_	&&
			&&
		CFG

CNT=1

EVT_PULSE=1&&

CR=1&&CNT <

CNT_CFG

CNT=1

Count	CNT=1	PULSE=1&& <CNTCFG
CNT >=CNT_CFG		PULSE=1&& <CNTCFG
CNT >=CNT_CFG
&&EVT_PULSE=1
NEXT_		EVT_ CNT
DIV=1
		Output
NEXT_
DIV=1

44	C6472/TCI6486 EMAC/MDIO	SPRUEF8F –March 2006 –Revised November 2010
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Texas Instruments TMS320TCI6486 manual Divide-by-N State Machine DSM, DSM State Transition Diagram

Contents

Users Guide Submit Documentation Feedback Preface Fifo Control Register Fifocontrol Appendix a Appendix BList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramSerial Management Interface Pins Signal DescriptionEMAC1EN Pin Description Value DescriptionIndustry Standards Compliance Statement Emac Clock Specifications Clock ControlMII Clocking Rmii ClockingMemory Map Gmii ClockingRgmii Clocking 5 S3MII ClockingEMAC0 Interface Selection Pins EMAC1 Interface Selection PinsSystem-Level Connections MACSEL020, MACSEL110, and EMAC1EN DecodingMedia Independent Interface MII Connections S3MII Rgmii RmiiEmac and Mdio Signals for MII Interface Signal Name DescriptionEmac and Mdio Signals for Rmii Interface Reduced Media Independent Interface Rmii ConnectionsRmtxen RmcrsdvGigabit Media Independent Interface Gmii Connections RmrxerEmac and Mdio Signals for Gmii Interface GmtclkEmac and Mdio Signals for Rgmii Interface RgtxcRgtxctl RgrefclkRgrxctl Ethernet Configuration with S3MII Interface Emac and Mdio Signals for S3MII Interface S3MII Multi-PHY Configuration S3MII Switch Configuration Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes DescriptionMultiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor QueuesTransmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Descriptor in C Structure FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRCNext Descriptor Pointer Buffer PointerBuffer Offset Buffer LengthEnd-of-Packet EOP Flag Ownership Owner FlagEnd-of-Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure FormatNext Descriptor Pointer Jabber Flag Oversize FlagFragment Flag Undersized FlagCommunications Port Programming Interface Cppi Ethernet Multicore Interrupt Combiner Emic ModuleEmic Block Diagram Pacing Block EvtoutTimed Delay State Machine Tdsm Tdsm State Transition DiagramDSM State Transition Diagram Divide-by-N State Machine DSMTransmit Pacer and Interrupt Combiner Tpic Transmit Pacer and Interrupt CombinerReceive Pacer and Interrupt Combiner Rpic Receive Pacer and Interrupt CombinerMdio Module Components Management Data Input/Output Mdio ModuleCommon Interrupt Combiner CIC PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register Example 3. Mdio Register Access Macros #define PHYREGreadregadr, phyadrEmac Module Emac Module ComponentsEmac Module Operational Overview Media Independent Interfaces Data ReceptionReceive Control Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3X Based Receive Buffer Flow ControlData Transmission Transmit ControlCRC Insertion Adaptive Performance Optimization APOBack Off Transmit Flow ControlReceive DMA Host Configuration Packet Receive OperationSpeed, Duplex, and Pause Frame Support Receive Channel EnablingHardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Receive Frame ClassificationPromiscuous Receive Mode Rxmbpenable BitsReceive Frame Treatment Summary Frame TreatmentTransmit DMA Host Configuration Packet Transmit OperationReceive Overrun Middle-of-Frame Overrun TreatmentTransmit Channel Teardown Receive and Transmit LatencyTransfer Node Priority Reset Considerations Software Reset ConsiderationsHardware Reset Considerations Rgmii TransmissionInitialization Enabling the EMAC/MDIO PeripheralEmic Module Initialization Mdio Module InitializationEmac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Receive Packet Completion InterruptsMdio Module Interrupt Events and Requests Host Error InterruptStatistics Interrupt Power Management User Access Completion InterruptEmulation Considerations Link Change InterruptEmulation Control Soft FreeEwintctl Registers Rpic RegistersRpcfg Registers Mdiouser Mdiolint Stat HostRpcfg Register Field Descriptions TimecfgCntcfg Bit FieldRpstat Registers Rpstat Register Field DescriptionsTpcfg Register Field Descriptions Tpic RegistersTpcfg Registers Prescalar Configuration Register Pscfg Tpstat RegistersTpstat Register Field Descriptions PrescalecfgAcronym Register Description IntroductionManagement Data Input/Output Mdio Registers Mdio Version Register Version Mdio Version Register Version Field DescriptionsModid Revmaj Revmin Bit Field Value DescriptionMdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Acknowledge Status Register Alive Field DescriptionsPHY Link Status Register Link PHY Link Status Register Link Field Descriptions31-2 Reserved Linkint Masked Userintraw Userint Maskset Mdio User Command Complete Interrupt Mask Clear Register MaskclearMdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsMdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon LinkselMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers FRAME1024TUP NetoctetsRxsofoverruns RxmofoverrunsTransmit Identification and Version Register Txidver TxidentRtlver Txmajorver Txminorver RtlverTxen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsRtlver Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtd Nrdy RxtdnchTransmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsMAC End-of-Interrupt Vector Register Maceoivector MAC End-of-Interrupt Vector Register MaceoivectorReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw Host Stat PendMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedMAC Interrupt Mask Set Register Macintmaskset Host Stat MaskHostmask StatmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen RxpromchRxmulten RxbroadenRxbroadch Rxmultch Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Maximum Length Register Rxmaxlen Field DescriptionsReceive Buffer Offset Register Rxbufferoffset Receive Buffer Offset Register RxbufferoffsetRxfilterthresh Reserved RXnFLOWTHRESH Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsRxfifoflowen CmdidleTxptype GIGMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsTxerrcode TxerrchRxerrcode RxerrchRgmiigig RgmiifullduplexEmulation Control Register Emcontrol Emulation Control Register Emcontrol Field DescriptionsSoft Free SoftFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field DescriptionsRxfifoflowthresh TxcellthreshMAC Configuration Register Macconfig MAC Configuration Register Macconfig Field DescriptionsTxcelldepth Rxcelldepth Addresstype Maccfig TxcelldepthSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 Bit Field Value Description 31-0 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Back Off Test Register Bofftest Field DescriptionsRndnum CollcountTransmit Pacing Algorithm Test Register Tpacetest PacevalPausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Match Channel Filt MACADDR0 MACADDR1 ValidMACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsTXnHDP RXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Transmit Channel n Completion Pointer Register TXnCPReceive Channel 0-7 Completion Pointer Register RXnCP Receive Channel n Completion Pointer Register RXnCPNetwork Statistics Registers Statistics Register Field DescriptionsGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register RxpauseframesReceive Oversized Frames Register Rxoversized Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsFiltered Receive Frames Register Rxfiltered Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register TxgoodframesBroadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 156 Appendix a Glossary Term Definition Appendix B Revision History Rfid Products ApplicationsDSP