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5.12 MAC End-of-Interrupt Vector Register (MACEOIVECTOR)
The MAC
Figure 54. MAC End-of-Interrupt Vector Register (MACEOIVECTOR)
31 | 5 | 4 | 0 |
Reserved |
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| MAC_EOI_VECTOR |
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LEGEND: R/W = Read/Write; R = Read only; |
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Table 48. MAC
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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4 | MAC_EOI_VECTOR |
| MAC |
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| The EOI_VECTOR[4:0] pins reflect the value written to this location one peripheral bus clock |
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| cycle after a write to this location. The EOI_WR signal is asserted for a single clock cycle after |
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| a latency of two peripheral bus clock cycles when a write is performed to this location. |
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106 | C6472/TCI6486 EMAC/MDIO | SPRUEF8F |
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