Texas Instruments TMS320TCI6486 Software Reset Considerations, Hardware Reset Considerations

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For example, for 1000-Mbps operation, these restrictions translate into the following rules:

•For the short-term average, each 64-byte memory read/write request from the EMAC must be serviced in no more than 0.512 μs.

•Any single latency event in request servicing can be no longer than (0.512 * TXCELLTHRESH) μs.

Bits [0-2] of the PRI_ALLOC register set the transfer node priority for EMAC0 in the device. Bits [12-14] of the PRI_ALLOC register set the transfer node priority for EMAC1 in the device. A value of 000b has the highest priority, while 111b has the lowest. The default priority assigned to EMAC0 and EMAC1 is 111b. It is important to have a balance between all peripherals. In most cases, the default priorities will not need adjustment.

2.15 Reset Considerations

2.15.1Software Reset Considerations

For information on the chip level reset capabilities of various peripherals, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual (SPRS300) or the TMS320C6472 Fixed-Point Digital Signal Processor data manual (SPRS612).

Within the peripheral itself, the EMAC component of the Ethernet MAC peripheral can be placed in a reset state by writing to the SOFTRESET register located in EMAC memory map. Writing a one to bit 0 of this register causes the EMAC logic to be reset, and the register values to be set to their default values. Software reset occurs when the receive and transmit DMA controllers are in an idle state to avoid locking up the configuration bus; it is the responsibility of the software to verify that there are no pending frames to be transferred. After writing a one to this bit, it may be polled to determine if the reset has occurred. A value of one indicates that the reset has not yet occurred. A value of zero indicates that a reset has occurred.

After a software reset operation, all the EMAC registers need to be re-initialized for proper data transmission.

Unlike the EMAC module, the MDIO, EMIC modules, and CPPI buffer managers cannot be placed in reset from a register inside their memory map.

2.15.2Hardware Reset Considerations

When a hardware reset occurs, the EMAC peripheral will have its register values reset, and all the sub-modules will return to their default state. After the hardware reset, the EMAC needs to be initialized before resuming its data transmission, as described in Section 2.16.

A hardware reset is the only means of recovering from the error interrupts (HOSTPEND), which are triggered by errors in packet buffer descriptors. Before doing a hardware reset, you should inspect the error codes in the MACSTATUS register. This register provides information about the software error type that needs correction. For more information on error interrupts, see Section 2.17.1.4.

2.15.3RGMII Transmission

On device reset, packet transmissions on the RGMII interface are precluded for 4096 transmit clock cycles after the RGMII link signal goes high. Transmission can be started only after 4096 cycles of transmit clock after the link signal goes high. Any packet transmission attempt within 4096 clock cycles of transmit clock will not cause an actual packet transmission over the RGMII interface. This restriction on packet transmissions calls for a delay in the packet transmission after device reset. An approximate delay of 2 ms after reset should be enough to start packet transmissions.

2.15.4S3MII Transmission

On device reset, packet transmissions on the S3MII interface are precluded for 4096 transmit clock cycles after the S3MII link signal goes high. Transmission can be started only after 4096 cycles of transmit clock after the link signal goes high. Any packet transmission attempt within 4096 clock cycles of transmit clock will not cause an actual packet transmission over the S3MII interface. This restriction on packet transmissions calls for a delay in the packet transmission after device reset. An approximate delay of 2 ms after reset should be enough to start packet transmissions.

64	C6472/TCI6486 EMAC/MDIO	SPRUEF8F –March 2006 –Revised November 2010
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