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EMAC Port Registers

5.30 MAC Status Register (MACSTATUS)

The MAC status register (MACSTATUS) is shown in Figure 72 and described in Table 66.

Figure 72. MAC Status Register (MACSTATUS)

31

30

24

IDLE

R-0

23

Reserved

R-0

20

19

18

16

TXERRCODE

Reserved

TXERRCH

R-0

 

R-0

 

R-0

15

12

11

10

8

RXERRCODE

Reserved

RXERRCH

R-0

 

 

R-0

 

R-0

 

7

5

4

3

2

1

0

Reserved

RDMIIGIG

RGMIIFULLDUPLEX

RXQOSACT

RXFLOWACT

TXFLOWACT

R-0R-xR-xR-0R-0R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 66. MAC Status Register (MACSTATUS) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31

IDLE

 

EMAC idle bit. This bit is set to 0 at reset; one clock after reset it goes to 1.

 

 

0

The EMAC is not idle

 

 

1

The EMAC is in the idle state

 

 

 

 

30-24

Reserved

0

Reserved

 

 

 

 

23-20

TXERRCODE

 

Transmit host error code. These bits indicate that EMAC detected transmit DMA related host

 

 

 

errors. The host should read this field after a host error interrupt (HOSTPEND) to determine

 

 

 

the error. Host error interrupts require a hardware reset in order to recover. A zero packet

 

 

 

length is an error, but it is not detected.

 

 

0

No error

 

 

1h

SOP error; the buffer is the first buffer in a packet, but the SOP bit is not set in software.

 

 

2h

Ownership bit not set in SOP buffer

 

 

3h

Zero next buffer descriptor pointer without EOP

 

 

4h

Zero buffer pointer

 

 

5h

Zero buffer length

 

 

6h

Packet length error (sum of buffers < packet length)

 

 

 

 

19

Reserved

0

Reserved

 

 

 

 

18-16

TXERRCH

0-3h

Transmit host error channel. These bits indicate on which transmit channel the host error

 

 

 

occurred. This field is cleared to 0 on a host read.

 

 

0

The host error occurred on transmit channel 0.

 

 

1h

The host error occurred on transmit channel 1.

 

 

2h

The host error occurred on transmit channel 2.

 

 

3h

The host error occurred on transmit channel 3.

 

 

4h

The host error occurred on transmit channel 4.

 

 

5h

The host error occurred on transmit channel 5.

 

 

6h

The host error occurred on transmit channel 6.

 

 

7h

The host error occurred on transmit channel 7.

 

 

 

 

SPRUEF8F –March 2006 –Revised November 2010

C6472/TCI6486 EMAC/MDIO

127

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Texas Instruments TMS320TCI6486 manual MAC Status Register Macstatus Field Descriptions, Txerrcode, Txerrch