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5.22 Receive Unicast Enable Set Register (RXUNICASTSET)
The receive unicast enable set register (RXUNICASTSET) is shown in Figure 64 and described in Table 58.
Figure 64. Receive Unicast Enable Set Register (RXUNICASTSET)
31 |
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| 16 |
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| Reserved |
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15 | 8 | 7 | 6 | 5 |
| 4 | 3 | 2 | 1 | 0 |
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Reserved |
| RXCH7EN | RXCH6EN | RXCH5EN |
| RXCH4EN | RXCH3EN | RXCH2EN | RXCH1EN | RXCH0EN |
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LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set;
Table 58. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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7 | RXCH7EN |
| Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May |
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| be read. |
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6 | RXCH6EN |
| Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May |
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| be read. |
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5 | RXCH5EN |
| Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May |
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| be read. |
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4 | RXCH4EN |
| Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May |
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| be read. |
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3 | RXCH3EN |
| Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May |
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| be read. |
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2 | RXCH2EN |
| Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May |
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| be read. |
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1 | RXCH1EN |
| Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May |
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| be read. |
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0 | RXCH0EN |
| Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May |
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| be read. |
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118 | C6472/TCI6486 EMAC/MDIO | SPRUEF8F |
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