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5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)
The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 65 and described in Table 59.
Figure 65. Receive Unicast Clear Register (RXUNICASTCLEAR)
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| 16 |
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| Reserved |
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15 | 8 | 7 | 6 | 5 |
| 4 | 3 | 2 | 1 | 0 |
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Reserved |
| RXCH7EN | RXCH6EN | RXCH5EN |
| RXCH4EN | RXCH3EN | RXCH2EN | RXCH1EN | RXCH0EN |
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LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear;
Table 59. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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7 | RXCH7EN |
| Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. |
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6 | RXCH6EN |
| Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. |
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5 | RXCH5EN |
| Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. |
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4 | RXCH4EN |
| Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. |
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3 | RXCH3EN |
| Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. |
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2 | RXCH2EN |
| Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. |
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1 | RXCH1EN |
| Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. |
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0 | RXCH0EN |
| Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. |
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SPRUEF8F | C6472/TCI6486 EMAC/MDIO | 119 |
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