Maskclear | Texas Instruments TMS320TCI6486 instruction

MDIO Registers

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4.11MDIO User Command Complete Interrupt Mask Clear Register

(USERINTMASKCLEAR)

The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 38 and described in Table 31.

Figure 38. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)

31			16
Reserved
R-0
15	2	1	0

Reserved		USERINT
Reserved		MASKCLEAR
		MASKCLEAR

R-0		R/WC-0

LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n= value after reset

Table 31. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)

Field Descriptions

Bit	Field	Value	Description

31-2	Reserved	0	Reserved

1-0	USERINTMASKCLEAR		MDIO user command complete interrupt mask clear for USERINTMASKED[1:0]
			respectively. Setting a bit to 1 will disable further user command complete interrupts for
			that particular USERACCESS register. Writing a 0 to this register has no effect.

86	C6472/TCI6486 EMAC/MDIO	SPRUEF8F –March 2006 –Revised November 2010
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Texas Instruments TMS320TCI6486 manual Mdio User Command Complete Interrupt Mask Clear Register, Maskclear

Contents

Users Guide Submit Documentation Feedback Preface Fifo Control Register Fifocontrol Appendix a Appendix B List of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram EMAC1EN Pin Description Serial Management Interface PinsSignal Description Value Description Industry Standards Compliance Statement MII Clocking Emac Clock SpecificationsClock Control Rmii Clocking Rgmii Clocking Memory MapGmii Clocking 5 S3MII Clocking System-Level Connections EMAC0 Interface Selection PinsEMAC1 Interface Selection Pins MACSEL020, MACSEL110, and EMAC1EN Decoding Media Independent Interface MII Connections S3MII Rgmii Rmii Emac and Mdio Signals for MII Interface Signal Name Description Rmtxen Emac and Mdio Signals for Rmii InterfaceReduced Media Independent Interface Rmii Connections Rmcrsdv Gigabit Media Independent Interface Gmii Connections Rmrxer Emac and Mdio Signals for Gmii Interface Gmtclk Rgtxctl Emac and Mdio Signals for Rgmii InterfaceRgtxc Rgrefclk Rgrxctl Ethernet Configuration with S3MII Interface Emac and Mdio Signals for S3MII Interface S3MII Multi-PHY Configuration S3MII Switch Configuration Ethernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes Description Multiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts SOP EOP Owner EOQ Tdown Pass Transmit Buffer Descriptor FormatExample 1. Transmit Descriptor in C Structure Format Cmplt CRC Buffer Offset Next Descriptor PointerBuffer Pointer Buffer Length End-of-Queue EOQ Flag End-of-Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Example 2. Receive Descriptor in C Structure Format Next Descriptor Pointer Fragment Flag Jabber FlagOversize Flag Undersized Flag Communications Port Programming Interface Cppi Ethernet Multicore Interrupt Combiner Emic Module Emic Block Diagram Pacing Block Evtout Timed Delay State Machine Tdsm Tdsm State Transition Diagram DSM State Transition Diagram Divide-by-N State Machine DSM Transmit Pacer and Interrupt Combiner Tpic Transmit Pacer and Interrupt Combiner Receive Pacer and Interrupt Combiner Rpic Receive Pacer and Interrupt Combiner Mdio Module Components Management Data Input/Output Mdio ModuleCommon Interrupt Combiner CIC Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY Monitoring Mdio Module Operational Overview Initializing the Mdio Module Reading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register Example 3. Mdio Register Access Macros #define PHYREGreadregadr, phyadr Emac Module Emac Module Components Emac Module Operational Overview Receive Control Media Independent InterfacesData Reception Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3X Based Receive Buffer Flow Control CRC Insertion Data TransmissionTransmit Control Adaptive Performance Optimization APO Back Off Transmit Flow Control Speed, Duplex, and Pause Frame Support Receive DMA Host ConfigurationPacket Receive Operation Receive Channel Enabling Hardware Receive QOS Support Host Free Buffer Tracking Receive Channel Teardown Receive Frame Classification Receive Frame Treatment Summary Promiscuous Receive ModeRxmbpenable Bits Frame Treatment Receive Overrun Transmit DMA Host ConfigurationPacket Transmit Operation Middle-of-Frame Overrun Treatment Transmit Channel Teardown Receive and Transmit LatencyTransfer Node Priority Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Rgmii Transmission Emic Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Mdio Module Initialization Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion Interrupts Mdio Module Interrupt Events and Requests Host Error InterruptStatistics Interrupt Emulation Considerations Power ManagementUser Access Completion Interrupt Link Change Interrupt Emulation Control Soft Free Rpcfg Registers Ewintctl RegistersRpic Registers Mdiouser Mdiolint Stat Host Cntcfg Rpcfg Register Field DescriptionsTimecfg Bit Field Rpstat Registers Rpstat Register Field Descriptions Tpcfg Register Field Descriptions Tpic RegistersTpcfg Registers Tpstat Register Field Descriptions Prescalar Configuration Register PscfgTpstat Registers Prescalecfg Acronym Register Description IntroductionManagement Data Input/Output Mdio Registers Modid Revmaj Revmin Mdio Version Register VersionMdio Version Register Version Field Descriptions Bit Field Value Description Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive PHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link PHY Link Status Register Link Field Descriptions 31-2 Reserved Linkint Masked Userintraw Userint Maskset Mdio User Command Complete Interrupt Mask Clear Register Maskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Phyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Linksel Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Rxsofoverruns FRAME1024TUPNetoctets Rxmofoverruns Rtlver Txmajorver Txminorver Transmit Identification and Version Register TxidverTxident Rtlver Txen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field Descriptions Rtlver Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Rxtd Nrdy Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions Rxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field Descriptions MAC End-of-Interrupt Vector Register Maceoivector MAC End-of-Interrupt Vector Register Maceoivector Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Unmasked Register Macintstatraw Host Stat Pend MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register Macintstatmasked Hostmask MAC Interrupt Mask Set Register MacintmasksetHost Stat Mask Statmask MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register Macintmaskclear Rxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen Rxpromch Rxmulten RxbroadenRxbroadch Rxmultch Receive Unicast Enable Set Register Rxunicastset RXCH7EN Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Receive Maximum Length Register Rxmaxlen Field Descriptions Receive Buffer Offset Register Rxbufferoffset Receive Buffer Offset Register Rxbufferoffset Rxfilterthresh Reserved RXnFLOWTHRESH Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Txptype RxfifoflowenCmdidle GIG Txerrcode MAC Status Register MacstatusMAC Status Register Macstatus Field Descriptions Txerrch Rgmiigig RxerrcodeRxerrch Rgmiifullduplex Soft Free Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Soft Rxfifoflowthresh Fifo Control Register FifocontrolFifo Control Register Fifocontrol Field Descriptions Txcellthresh Txcelldepth Rxcelldepth Addresstype Maccfig MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Txcelldepth Soft Reset Register Softreset Soft Reset Register Softreset Field Descriptions MACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 Bit Field Value Description 31-0 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field Descriptions Rndnum Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Collcount Transmit Pacing Algorithm Test Register Tpacetest Paceval Pausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field Descriptions Valid Match Channel Filt MACADDR0 MACADDR1 MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid MACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex MAC Index Register Macindex Field Descriptions TXnHDP RXnHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Transmit Channel n Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCP Receive Channel n Completion Pointer Register RXnCP Good Receive Frames Register Rxgoodframes Network Statistics RegistersStatistics Register Field Descriptions Broadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register Rxpauseframes Receive Undersized Frames Register Rxundersized Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Frame Fragments Register Rxfragments Receive Octet Frames Register Rxoctets Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Good Transmit Frames Register Txgoodframes Pause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register Txdeferred Transmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 156 Appendix a Glossary Term Definition Appendix B Revision History Rfid Products ApplicationsDSP