Texas Instruments TMS320TCI6486 manual Receive and Transmit Latency, Transfer Node Priority

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•Initialize the TXnHDP registers to zero.

•Enable the desired transmit interrupts using the TXINTMASKSET and TXINTMASKCLEAR registers.

•Set the appropriate configuration bits in the MACCONTROL register.

•Set up the transmit channel(s) buffer descriptors in host memory.

•Enable the transmit DMA controller by setting the TXEN bit in the TXCONTROL register.

•Write the appropriate TXnHDP registers with the pointer to the first descriptor to start transmit operations.

2.12.2Transmit Channel Teardown

The host commands a transmit channel teardown by writing the channel number to the TXTEARDOWN register. When a teardown command is issued to an enabled transmit channel, the following occurs:

•Any frame currently in transmission completes normally.

•The TDOWNCMPLT flag is set in the next SOP buffer descriptor in the chain, if there is one.

•The channel head descriptor pointer is cleared.

•A transmit interrupt is issued, informing the host of the channel teardown.

•The corresponding TXnCP register contains the value FFFF FFFCh.

•The host should acknowledge a teardown interrupt with an FFFF FFFCh acknowledge value.

Channel teardown may be commanded on any channel at any time. The host is informed of the teardown completion by the set teardown complete buffer descriptor bit (TDOWNCMPLT). The EMAC does not clear any channel enables due to a teardown command. A teardown command to an inactive channel issues an interrupt that software should acknowledge with an FFFF FFFCh acknowledge value to TXnCP (note that there is no buffer descriptor). Software may read the interrupt acknowledge location (TXnCP) to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh if the interrupt was due to a teardown command.

2.13 Receive and Transmit Latency

The transmit FIFO contains twenty four 64-byte cells, and the receive FIFO contains sixty eight 64-byte cells. The EMAC begins transmission of a packet on the wire after TXCELLTHRESH cells (configurable through the FIFOCONTROL register) or a complete packet are available in the FIFO.

Transmit underrun cannot occur for packet sizes of TXCELLTHRESH times 64 bytes (or less). For larger packet sizes, transmit underrun can occur if the memory latency is greater than the time required to transmit a 64-byte cell on the wire; this is 0.512 μs in 1 Gbit mode, 5.12 μs in 100 Mbps mode, and 51.2 μs in 10 Mbps mode. The memory latency time includes all buffer descriptor reads for the entire cell data.

The EMAC transmit FIFO uses 24 cells; thus, underrun cannot happen for a normal size packet (less than 1536 packet bytes). Cell transmission can be configured to start only after an entire packet is contained in the FIFO; for a maximum-size packet, set the TXCELLTHRESH field to the maximum possible value of 24.

Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a 64-byte cell on the wire (0.512 μs in 1 Gbps mode, 5.12 μs in 100 Mbps mode, or 51.2μs in 10 Mbps mode). The latency time includes any required buffer descriptor reads for the cell data.

Latency to system'sinternal and external RAM can be controlled through the use of the transfer node priority allocation register in the TCI6486/C6472 devices. Latency to descriptor RAM is low because RAM is local to the EMAC, as it is part of the CPPI buffer manager.

2.14 Transfer Node Priority

The TCI6486/C6472 devices contain a system-level priority allocation register (PRI_ALLOC) that sets the priority of the transfer node used in issuing memory transfer requests to system memory.

Although the EMAC has internal FIFOs to help alleviate memory transfer arbitration problems, the average transfer rate of data read and written by the EMAC to internal or external DSP memory must be at least equal to the Ethernet wire rate. In addition, the internal FIFO system cannot withstand a single memory latency event greater than the time it takes to fill or empty a TXCELLTHRESH number of internal 64-byte FIFO cells.

SPRUEF8F –March 2006 –Revised November 2010	C6472/TCI6486 EMAC/MDIO	63
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