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EMAC Port Registers

5.31 Emulation Control Register (EMCONTROL)

The emulation control register (EMCONTROL) is shown in Figure 73 and described in Table 67.

Figure 73. Emulation Control Register (EMCONTROL)

31			16
Reserved

R-0
15	2	1	0

Reserved		SOFT	FREE

R-0		R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 67. Emulation Control Register (EMCONTROL) Field Descriptions

Bit	Field	Value	Description

31-2	Reserved	0	Reserved

1	SOFT		Emulation soft bit

0	FREE		Emulation free bit

SPRUEF8F –March 2006 –Revised November 2010	C6472/TCI6486 EMAC/MDIO	129
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Texas Instruments TMS320TCI6486 manual Emulation Control Register Emcontrol, Soft Free

Contents

Users Guide Submit Documentation Feedback Preface Fifo Control Register Fifocontrol Appendix B Appendix a List of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Signal Description Serial Management Interface PinsEMAC1EN Pin Description Value Description Industry Standards Compliance Statement Clock Control Emac Clock SpecificationsMII Clocking Rmii Clocking Gmii Clocking Memory MapRgmii Clocking 5 S3MII Clocking EMAC1 Interface Selection Pins EMAC0 Interface Selection PinsSystem-Level Connections MACSEL020, MACSEL110, and EMAC1EN Decoding S3MII Rgmii Rmii Media Independent Interface MII Connections Signal Name Description Emac and Mdio Signals for MII Interface Reduced Media Independent Interface Rmii Connections Emac and Mdio Signals for Rmii InterfaceRmtxen Rmcrsdv Rmrxer Gigabit Media Independent Interface Gmii Connections Gmtclk Emac and Mdio Signals for Gmii Interface Rgtxc Emac and Mdio Signals for Rgmii InterfaceRgtxctl Rgrefclk Rgrxctl Ethernet Configuration with S3MII Interface Emac and Mdio Signals for S3MII Interface S3MII Multi-PHY Configuration S3MII Switch Configuration Ethernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Field Bytes Description Multiple Access Protocol Programming Interface Packet Buffer DescriptorsBasic Descriptors Transmit and Receive Descriptor Queues Typical Descriptor Linked List Transmit and Receive Emac Interrupts Example 1. Transmit Descriptor in C Structure Format Transmit Buffer Descriptor FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRC Buffer Pointer Next Descriptor PointerBuffer Offset Buffer Length Ownership Owner Flag End-of-Packet EOP FlagEnd-of-Queue EOQ Flag Teardown Complete Tdowncmplt Flag Example 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor Format Next Descriptor Pointer Oversize Flag Jabber FlagFragment Flag Undersized Flag Ethernet Multicore Interrupt Combiner Emic Module Communications Port Programming Interface Cppi Emic Block Diagram Evtout Pacing Block Tdsm State Transition Diagram Timed Delay State Machine Tdsm Divide-by-N State Machine DSM DSM State Transition Diagram Transmit Pacer and Interrupt Combiner Transmit Pacer and Interrupt Combiner Tpic Receive Pacer and Interrupt Combiner Receive Pacer and Interrupt Combiner Rpic Management Data Input/Output Mdio Module Common Interrupt Combiner CICMdio Module Components Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY Monitoring Initializing the Mdio Module Mdio Module Operational Overview Example of Mdio Register Access Code Writing Data to a PHY RegisterReading Data From a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access Macros Emac Module Components Emac Module Emac Module Operational Overview Data Reception Media Independent InterfacesReceive Control Receive Inter-Frame Interval Ieee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control Transmit Control Data TransmissionCRC Insertion Adaptive Performance Optimization APO Transmit Flow Control Back Off Packet Receive Operation Receive DMA Host ConfigurationSpeed, Duplex, and Pause Frame Support Receive Channel Enabling Host Free Buffer Tracking Hardware Receive QOS Support Receive Frame Classification Receive Channel Teardown Rxmbpenable Bits Promiscuous Receive ModeReceive Frame Treatment Summary Frame Treatment Packet Transmit Operation Transmit DMA Host ConfigurationReceive Overrun Middle-of-Frame Overrun Treatment Receive and Transmit Latency Transfer Node PriorityTransmit Channel Teardown Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Rgmii Transmission Enabling the EMAC/MDIO Peripheral InitializationEmic Module Initialization Mdio Module Initialization Emac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportTransmit Packet Completion Interrupts Receive Packet Completion Interrupts Host Error Interrupt Statistics InterruptMdio Module Interrupt Events and Requests User Access Completion Interrupt Power ManagementEmulation Considerations Link Change Interrupt Soft Free Emulation Control Rpic Registers Ewintctl RegistersRpcfg Registers Mdiouser Mdiolint Stat Host Timecfg Rpcfg Register Field DescriptionsCntcfg Bit Field Rpstat Register Field Descriptions Rpstat Registers Tpic Registers Tpcfg RegistersTpcfg Register Field Descriptions Tpstat Registers Prescalar Configuration Register PscfgTpstat Register Field Descriptions Prescalecfg Introduction Management Data Input/Output Mdio RegistersAcronym Register Description Mdio Version Register Version Field Descriptions Mdio Version Register VersionModid Revmaj Revmin Bit Field Value Description Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register Link Field Descriptions PHY Link Status Register Link 31-2 Reserved Linkint Masked Userintraw Userint Maskset Maskclear Mdio User Command Complete Interrupt Mask Clear Register Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Netoctets FRAME1024TUPRxsofoverruns Rxmofoverruns Txident Transmit Identification and Version Register TxidverRtlver Txmajorver Txminorver Rtlver Transmit Control Register Txcontrol Transmit Control Register Txcontrol Field DescriptionsTxen Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register Txteardown Receive Identification and Version Register Rxidver RxidentRtlver Rxmajorver Rxminorver Receive Control Register Rxcontrol Receive Control Register Rxcontrol Field DescriptionsRxen Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtd Nrdy Rxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register Macinvector MAC End-of-Interrupt Vector Register Maceoivector MAC End-of-Interrupt Vector Register Maceoivector Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear Host Stat Pend MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register Macintstatmasked Host Stat Mask MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register Macintmaskclear Rxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen Rxpromch Rxbroaden RxbroadchRxmulten Rxmultch RXCH7EN Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register Rxbufferoffset Receive Buffer Offset Register Rxbufferoffset Rxfilterthresh Reserved RXnFLOWTHRESH Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Cmdidle RxfifoflowenTxptype GIG MAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusTxerrcode Txerrch Rxerrch RxerrcodeRgmiigig Rgmiifullduplex Emulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolSoft Free Soft Fifo Control Register Fifocontrol Field Descriptions Fifo Control Register FifocontrolRxfifoflowthresh Txcellthresh MAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigTxcelldepth Rxcelldepth Addresstype Maccfig Txcelldepth Soft Reset Register Softreset Field Descriptions Soft Reset Register Softreset MAC Source Address Low Bytes Register Macsrcaddrlo MACSRCADDR0 MACSRCADDR1MACSRCADDR0 MAC Source Address High Bytes Register Macsrcaddrhi MACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5MACSRCADDR2 MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 1 MACHASH1 Field DescriptionsBit Field Value Description 31-0 MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2 Back Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestRndnum Collcount Paceval Transmit Pacing Algorithm Test Register Tpacetest Receive Pause Timer Register Rxpause Receive Pause Timer Register Rxpause Field DescriptionsPausetimer Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register Txpause MAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Match Channel Filt MACADDR0 MACADDR1 Valid MAC Address High Bytes Register Macaddrhi MACADDR2 MACADDR3 MACADDR4 MACADDR5MACADDR2 MAC Index Register Macindex Field Descriptions MAC Index Register Macindex TXnHDP RXnHDP Transmit Channel n Completion Pointer Register TXnCP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel n Completion Pointer Register RXnCP Receive Channel 0-7 Completion Pointer Register RXnCP Statistics Register Field Descriptions Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register Rxbcastframes Receive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register Rxpauseframes Receive Jabber Frames Register Rxjabber Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Receive QOS Filtered Frames Register Rxqosfiltered Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register Txgoodframes Multicast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register Txdeferred Transmit Underrun Error Register Txunderrun Transmit Multiple Collision Frames Register TxmulticollTransmit Late Collision Frames Register Txlatecoll Transmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets 156 Appendix a Glossary Term Definition Appendix B Revision History Products Applications DSPRfid