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Texas Instruments TMS320TCI6486 manual MAC Index Register Macindex

Models: TMS320TCI6486

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EMAC Port Registers

5.45 MAC Index Register (MACINDEX)

The MAC index register (MACINDEX) is shown in Figure 87 and described in Table 81.

Figure 87. MAC Index Register (MACINDEX)

31			16
	Reserved

	R-0
15	5	4	0

Reserved			MACINDEX

R-0			R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 81. MAC Index Register (MACINDEX) Field Descriptions

Bit	Field	Value	Description

31-5	Reserved	0	Reserved

4-0	MACINDEX		MAC address index. The host must write the index into the RX ADDR RAM in the MACINDEX field,
			followed by the upper 32-bits of address, followed by the lower 16-bits of address (with control bits).
			The 53-bit indexed ram location is written when the low location is written. All 32 address RAM
			locations must be initialized prior to enabling packet reception.

SPRUEF8F –March 2006 –Revised November 2010	C6472/TCI6486 EMAC/MDIO	143
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Texas Instruments TMS320TCI6486 manual MAC Index Register Macindex Field Descriptions

Contents

Users Guide Submit Documentation Feedback Preface Fifo Control Register Fifocontrol Appendix B Appendix aList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramValue Description Serial Management Interface PinsSignal Description EMAC1EN Pin DescriptionIndustry Standards Compliance Statement Rmii Clocking Emac Clock SpecificationsClock Control MII Clocking5 S3MII Clocking Memory MapGmii Clocking Rgmii ClockingMACSEL020, MACSEL110, and EMAC1EN Decoding EMAC0 Interface Selection PinsEMAC1 Interface Selection Pins System-Level ConnectionsS3MII Rgmii Rmii Media Independent Interface MII ConnectionsSignal Name Description Emac and Mdio Signals for MII InterfaceRmcrsdv Emac and Mdio Signals for Rmii InterfaceReduced Media Independent Interface Rmii Connections RmtxenRmrxer Gigabit Media Independent Interface Gmii ConnectionsGmtclk Emac and Mdio Signals for Gmii InterfaceRgrefclk Emac and Mdio Signals for Rgmii InterfaceRgtxc RgtxctlRgrxctl Ethernet Configuration with S3MII Interface Emac and Mdio Signals for S3MII Interface S3MII Multi-PHY Configuration S3MII Switch Configuration Field Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame DescriptionMultiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Transmit and Receive Descriptor Queues Typical Descriptor Linked ListTransmit and Receive Emac Interrupts Cmplt CRC Transmit Buffer Descriptor FormatExample 1. Transmit Descriptor in C Structure Format SOP EOP Owner EOQ Tdown PassBuffer Length Next Descriptor PointerBuffer Pointer Buffer OffsetTeardown Complete Tdowncmplt Flag End-of-Packet EOP FlagOwnership Owner Flag End-of-Queue EOQ FlagExample 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor FormatNext Descriptor Pointer Undersized Flag Jabber FlagOversize Flag Fragment FlagEthernet Multicore Interrupt Combiner Emic Module Communications Port Programming Interface CppiEmic Block Diagram Evtout Pacing BlockTdsm State Transition Diagram Timed Delay State Machine TdsmDivide-by-N State Machine DSM DSM State Transition DiagramTransmit Pacer and Interrupt Combiner Transmit Pacer and Interrupt Combiner TpicReceive Pacer and Interrupt Combiner Receive Pacer and Interrupt Combiner RpicMdio Module Components Management Data Input/Output Mdio ModuleCommon Interrupt Combiner CIC Active PHY Monitoring PHY Register User AccessMdio Clock Generator Global PHY Detection and Link State MonitoringInitializing the Mdio Module Mdio Module Operational OverviewReading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access MacrosEmac Module Components Emac ModuleEmac Module Operational Overview Receive Inter-Frame Interval Media Independent InterfacesData Reception Receive ControlIeee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlAdaptive Performance Optimization APO Data TransmissionTransmit Control CRC InsertionTransmit Flow Control Back OffReceive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Speed, Duplex, and Pause Frame SupportHost Free Buffer Tracking Hardware Receive QOS SupportReceive Frame Classification Receive Channel TeardownFrame Treatment Promiscuous Receive ModeRxmbpenable Bits Receive Frame Treatment SummaryMiddle-of-Frame Overrun Treatment Transmit DMA Host ConfigurationPacket Transmit Operation Receive OverrunTransmit Channel Teardown Receive and Transmit LatencyTransfer Node Priority Rgmii Transmission Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsMdio Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Emic Module InitializationEmac Module Initialization Receive Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Transmit Packet Completion InterruptsMdio Module Interrupt Events and Requests Host Error InterruptStatistics Interrupt Link Change Interrupt Power ManagementUser Access Completion Interrupt Emulation ConsiderationsSoft Free Emulation ControlMdiouser Mdiolint Stat Host Ewintctl RegistersRpic Registers Rpcfg RegistersBit Field Rpcfg Register Field DescriptionsTimecfg CntcfgRpstat Register Field Descriptions Rpstat RegistersTpcfg Register Field Descriptions Tpic RegistersTpcfg Registers Prescalecfg Prescalar Configuration Register PscfgTpstat Registers Tpstat Register Field DescriptionsAcronym Register Description IntroductionManagement Data Input/Output Mdio Registers Bit Field Value Description Mdio Version Register VersionMdio Version Register Version Field Descriptions Modid Revmaj RevminMdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link Field Descriptions PHY Link Status Register Link31-2 Reserved Linkint Masked Userintraw Userint Maskset Maskclear Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb PhyadrmonMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Rxmofoverruns FRAME1024TUPNetoctets RxsofoverrunsRtlver Transmit Identification and Version Register TxidverTxident Rtlver Txmajorver TxminorverTxen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownRtlver Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions Rxtd NrdyTransmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorMAC End-of-Interrupt Vector Register Maceoivector MAC End-of-Interrupt Vector Register MaceoivectorReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHost Stat Pend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedStatmask MAC Interrupt Mask Set Register MacintmasksetHost Stat Mask HostmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen RxcafenRxmulten RxbroadenRxbroadch Rxmultch RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Receive Buffer Offset Register RxbufferoffsetRxfilterthresh Reserved RXnFLOWTHRESH Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolGIG RxfifoflowenCmdidle TxptypeTxerrch MAC Status Register MacstatusMAC Status Register Macstatus Field Descriptions TxerrcodeRgmiifullduplex RxerrcodeRxerrch RgmiigigSoft Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Soft FreeTxcellthresh Fifo Control Register FifocontrolFifo Control Register Fifocontrol Field Descriptions RxfifoflowthreshTxcelldepth MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Txcelldepth Rxcelldepth Addresstype MaccfigSoft Reset Register Softreset Field Descriptions Soft Reset Register SoftresetMACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 Bit Field Value Description 31-0 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2Collcount Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions RndnumPaceval Transmit Pacing Algorithm Test Register TpacetestPausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register TxpauseValid MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid Match Channel Filt MACADDR0 MACADDR1MACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex Field Descriptions MAC Index Register MacindexTXnHDP RXnHDP Transmit Channel n Completion Pointer Register TXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPReceive Channel n Completion Pointer Register RXnCP Receive Channel 0-7 Completion Pointer Register RXnCPBroadcast Receive Frames Register Rxbcastframes Network Statistics RegistersStatistics Register Field Descriptions Good Receive Frames Register RxgoodframesPause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Multicast Receive Frames Register RxmcastframesReceive Frame Fragments Register Rxfragments Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedGood Transmit Frames Register Txgoodframes Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsDeferred Transmit Frames Register Txdeferred Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Pause Transmit Frames Register TxpauseframesTransmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 156 Appendix a Glossary Term Definition Appendix B Revision History Rfid Products ApplicationsDSP