Texas Instruments TMS320TCI6486 Fifo Control Register Fifocontrol, Rxfifoflowthresh, Txcellthresh

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5.32 FIFO Control Register (FIFOCONTROL)

The FIFO control register (FIFOCONTROL) is shown in Figure 74 and described in Table 68.

Figure 74. FIFO Control Register (FIFOCONTROL)

31	23	22		16
Reserved			RXFIFOFLOWTHRESH
R-0			R/W-2
15		5	4	0
Reserved			TXCELLTHRESH
R-0			R/W-24

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 68. FIFO Control Register (FIFOCONTROL) Field Descriptions

Bit	Field	Value	Description
31-23	Reserved	0	Reserved
22-16	RXFIFOFLOWTHRESH		Receive FIFO flow control threshold. Occupancy of the receive FIFO when Receive FIFO
			flow control is triggered (if enabled). The default value is 0x2, which means that receive
			FIFO flow control is triggered when the occupancy of the FIFO reaches two cells.
15-5	Reserved	0	Reserved
4-0	TXCELLTHRESH		Transmit FIFO cell threshold. Indicates the number of 64-byte packet cells required to be
			in the transmit FIFO before the packet transfer is initiated. Packets with fewer cells are
			initiated when the complete packet is contained in the FIFO. This value must be greater
			then or equal to 2 and less than or equal to 24.

130	C6472/TCI6486 EMAC/MDIO	SPRUEF8F –March 2006 –Revised November 2010
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