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Texas Instruments TMS320TCI6486 manual Emic Block Diagram

Models: TMS320TCI6486

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EMAC Functional Architecture

– Interrupt combiner

•Common Interrupt Combiner (CIC)

•Prescaler

•Registers

•CFG peripheral bus interface

EMAC interrupts(18)

MDIO interrupts(2)

Peripheralbus reset

Peripheralbus

Peripheralbus clock

Figure 14. EMIC Block Diagram

TXpacerandinterruptcombiner

RXpacerandinterruptcombiner

Commoninterruptcombiner

TXpacerandinterruptcombiner

RXpacerandinterruptcombiner

Commoninterruptcombiner

TXpacerandinterruptcombiner

RXpacerandinterruptcombiner

Commoninterruptcombiner

TXpacerandinterruptcombiner

RXpacerandinterruptcombiner

Commoninterruptcombiner

TXpacerandinterruptcombiner

RXpacerandinterruptcombiner

Commoninterruptcombiner

TXpacerandinterruptcombiner

RXpacerandinterruptcombiner

Commoninterruptcombiner

Registers

PS_TICK

Prescaler

MACTXINT0

MACRXINT0 ToGEM0

MACINT0

MACTXINT1

MACRXINT1 ToGEM1

MACINT1

MACTXINT2

MACRXINT2 ToGEM2

MACINT2

MACTXINT3

MACRXINT3 ToGEM3

MACINT3

MACTXINT4

MACRXINT4 ToGEM4

MACINT4

MACTXINT5

MACRXINT5 ToGEM5

MACINT5

SPRUEF8F –March 2006 –Revised November 2010	C6472/TCI6486 EMAC/MDIO	41
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Texas Instruments TMS320TCI6486 manual Emic Block Diagram

Contents

Users Guide Submit Documentation Feedback Preface Fifo Control Register Fifocontrol Appendix B Appendix aList of Figures Transmit Interrupt Mask Set Register Txintmaskset List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramSignal Description Serial Management Interface PinsEMAC1EN Pin Description Value DescriptionIndustry Standards Compliance Statement Clock Control Emac Clock SpecificationsMII Clocking Rmii ClockingGmii Clocking Memory MapRgmii Clocking 5 S3MII ClockingEMAC1 Interface Selection Pins EMAC0 Interface Selection PinsSystem-Level Connections MACSEL020, MACSEL110, and EMAC1EN DecodingS3MII Rgmii Rmii Media Independent Interface MII ConnectionsSignal Name Description Emac and Mdio Signals for MII InterfaceReduced Media Independent Interface Rmii Connections Emac and Mdio Signals for Rmii InterfaceRmtxen RmcrsdvRmrxer Gigabit Media Independent Interface Gmii ConnectionsGmtclk Emac and Mdio Signals for Gmii InterfaceRgtxc Emac and Mdio Signals for Rgmii InterfaceRgtxctl RgrefclkRgrxctl Ethernet Configuration with S3MII Interface Emac and Mdio Signals for S3MII Interface S3MII Multi-PHY Configuration S3MII Switch Configuration Ethernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Field Bytes DescriptionMultiple Access Protocol Basic Descriptors Programming InterfacePacket Buffer Descriptors Transmit and Receive Descriptor Queues Typical Descriptor Linked ListTransmit and Receive Emac Interrupts Example 1. Transmit Descriptor in C Structure Format Transmit Buffer Descriptor FormatSOP EOP Owner EOQ Tdown Pass Cmplt CRCBuffer Pointer Next Descriptor PointerBuffer Offset Buffer LengthOwnership Owner Flag End-of-Packet EOP FlagEnd-of-Queue EOQ Flag Teardown Complete Tdowncmplt FlagExample 2. Receive Descriptor in C Structure Format Receive Buffer Descriptor FormatNext Descriptor Pointer Oversize Flag Jabber FlagFragment Flag Undersized FlagEthernet Multicore Interrupt Combiner Emic Module Communications Port Programming Interface CppiEmic Block Diagram Evtout Pacing BlockTdsm State Transition Diagram Timed Delay State Machine TdsmDivide-by-N State Machine DSM DSM State Transition DiagramTransmit Pacer and Interrupt Combiner Transmit Pacer and Interrupt Combiner TpicReceive Pacer and Interrupt Combiner Receive Pacer and Interrupt Combiner RpicMdio Module Components Management Data Input/Output Mdio ModuleCommon Interrupt Combiner CIC Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY MonitoringInitializing the Mdio Module Mdio Module Operational OverviewReading Data From a PHY Register Example of Mdio Register Access CodeWriting Data to a PHY Register #define PHYREGreadregadr, phyadr Example 3. Mdio Register Access MacrosEmac Module Components Emac ModuleEmac Module Operational Overview Data Reception Media Independent InterfacesReceive Control Receive Inter-Frame IntervalIeee 802.3X Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlTransmit Control Data TransmissionCRC Insertion Adaptive Performance Optimization APOTransmit Flow Control Back OffPacket Receive Operation Receive DMA Host ConfigurationSpeed, Duplex, and Pause Frame Support Receive Channel EnablingHost Free Buffer Tracking Hardware Receive QOS SupportReceive Frame Classification Receive Channel TeardownRxmbpenable Bits Promiscuous Receive ModeReceive Frame Treatment Summary Frame TreatmentPacket Transmit Operation Transmit DMA Host ConfigurationReceive Overrun Middle-of-Frame Overrun TreatmentTransmit Channel Teardown Receive and Transmit LatencyTransfer Node Priority Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Rgmii TransmissionEnabling the EMAC/MDIO Peripheral InitializationEmic Module Initialization Mdio Module InitializationEmac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportTransmit Packet Completion Interrupts Receive Packet Completion InterruptsMdio Module Interrupt Events and Requests Host Error InterruptStatistics Interrupt User Access Completion Interrupt Power ManagementEmulation Considerations Link Change InterruptSoft Free Emulation ControlRpic Registers Ewintctl RegistersRpcfg Registers Mdiouser Mdiolint Stat HostTimecfg Rpcfg Register Field DescriptionsCntcfg Bit FieldRpstat Register Field Descriptions Rpstat RegistersTpcfg Register Field Descriptions Tpic RegistersTpcfg Registers Tpstat Registers Prescalar Configuration Register PscfgTpstat Register Field Descriptions PrescalecfgAcronym Register Description IntroductionManagement Data Input/Output Mdio Registers Mdio Version Register Version Field Descriptions Mdio Version Register VersionModid Revmaj Revmin Bit Field Value DescriptionMdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link Field Descriptions PHY Link Status Register Link31-2 Reserved Linkint Masked Userintraw Userint Maskset Maskclear Mdio User Command Complete Interrupt Mask Clear RegisterMdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon LinkselMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Network Statistics Registers Netoctets FRAME1024TUPRxsofoverruns RxmofoverrunsTxident Transmit Identification and Version Register TxidverRtlver Txmajorver Txminorver RtlverTxen Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownRtlver Rxmajorver Rxminorver Receive Identification and Version Register RxidverRxident Rxen Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtd Nrdy RxtdnchTransmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorMAC End-of-Interrupt Vector Register Maceoivector MAC End-of-Interrupt Vector Register MaceoivectorReceive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHost Stat Pend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Masked Register MacintstatmaskedHost Stat Mask MAC Interrupt Mask Set Register MacintmasksetHostmask StatmaskMAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Clear Register MacintmaskclearRxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen RxpromchRxmulten RxbroadenRxbroadch Rxmultch RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Receive Buffer Offset Register RxbufferoffsetRxfilterthresh Reserved RXnFLOWTHRESH Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolCmdidle RxfifoflowenTxptype GIGMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusTxerrcode TxerrchRxerrch RxerrcodeRgmiigig RgmiifullduplexEmulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolSoft Free SoftFifo Control Register Fifocontrol Field Descriptions Fifo Control Register FifocontrolRxfifoflowthresh TxcellthreshMAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigTxcelldepth Rxcelldepth Addresstype Maccfig TxcelldepthSoft Reset Register Softreset Field Descriptions Soft Reset Register SoftresetMACSRCADDR0 MAC Source Address Low Bytes Register MacsrcaddrloMACSRCADDR0 MACSRCADDR1 MACSRCADDR2 MAC Source Address High Bytes Register MacsrcaddrhiMACSRCADDR2 MACSRCADDR3 MACSRCADDR4 MACSRCADDR5 Bit Field Value Description 31-0 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 2 MACHASH2Back Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestRndnum CollcountPaceval Transmit Pacing Algorithm Test Register TpacetestPausetimer Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions Transmit Pause Timer Register TxpauseMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Match Channel Filt MACADDR0 MACADDR1 ValidMACADDR2 MAC Address High Bytes Register MacaddrhiMACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Index Register Macindex Field Descriptions MAC Index Register MacindexTXnHDP RXnHDP Transmit Channel n Completion Pointer Register TXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPReceive Channel n Completion Pointer Register RXnCP Receive Channel 0-7 Completion Pointer Register RXnCPStatistics Register Field Descriptions Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsMulticast Receive Frames Register Rxmcastframes Pause Receive Frames Register RxpauseframesReceive Jabber Frames Register Rxjabber Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsReceive QOS Filtered Frames Register Rxqosfiltered Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Good Transmit Frames Register TxgoodframesMulticast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets 156 Appendix a Glossary Term Definition Appendix B Revision History Rfid Products ApplicationsDSP